AS4LC8M8S0-8FTC View Datasheet(PDF) - Alliance Semiconductor
Part Name
Description
MFG CO.
'AS4LC8M8S0-8FTC' PDF : 24 Pages View PDF
AS4LC4M16S0
AS4LC16M4S0
®
Mode register set command waveform
CLK
CMD
PRE
tRP
MRS can be issued only when both banks are idle.
MRS
ACT
tRSC(min)
Precharge waveforms
Precharge can be asserted after tRAS (min). The selected bank will enter the idle state after tRP.. The earliest assertion of the
precharge command without losing any burst data is show below.
(normal write; BL = 4)
CLK
CMD
DQ
CLK
WE
D0
D1
D2
D3
PRE
(normal read; BL = 4)
CMD
Read data
PRE
DQ(CL2)
DQ(CL3)
Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3
Auto precharge waveforms
A10 controls the selection of auto precharge during the read or write command cycle.
(write with auto precharge; BL = 4)
CLK
CMD
WE
DQ
D0
D1
D2
D3
Auto precharge starts*
(read with auto precharge; BL = 4)
CLK
CMD
DQ(CL2)
DQ(CL3)
Read data
Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3
Auto precharge starts*
* The row active command of the precharge bank can be issued after tRP from this point. At burst read/write with auto precharge, CAS interrupt of the same
bank is illegal; other bank is described below.
12
ALLIANCE SEMICONDUCTOR
7/5/00
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