AS4LC8M8S0-8FTC View Datasheet(PDF) - Alliance Semiconductor
Part Name
Description
MFG CO.
'AS4LC8M8S0-8FTC' PDF : 24 Pages View PDF
AS4LC4M16S0
AS4LC16M4S0
®
write interrupted by write (BL = 4)
CLK
CMD
tCCD
Write data Write data
ADD
A0
B0
DQ
DA0
DB0
DB1
DB2
DB3
tCDL
tCCD = CAS to CAS delay (= 1 CLK)
tCDL = last address in to new column addres delay (= 1 CLK)
CLK
CMD
ADD
tCCD
Write data Read data
A
B
write interrupted by read (CL = 2, BL = 4)
DQ (CL2)
DA0
DQ (CL3)
DA0
tCDL
tCCD = CAS to CAS delay (= 1 CLK)
tCDL = last address in to new column addres delay (= 1 CLK)
QB0
QB1
QB2
QB3
QB0
QB1
QB2
QB3
read interrupted by write (CL = 3, BL = 4)
CLK
CMD
DQM
Read data
Write data*
DQ
* To prevent bus contention, maintain a gap between data in and data out.
Q0
D0
D1
D2
D3
Burst termination
Burst operations may be terminated with a Read, Write, Burst Stop, or Precharge command. When Burst Stop is asserted
during the read cycle, burst read data is terminated and the data bus goes to High Z after CAS latency. When Burst Stop is
asserted during the write cycle, burst write data is terminated and the databus goes to High Z simultaneously.
Burst stop command waveform, read cycle
CLK
CMD
Read data
DQ (CL = 2)
DQ (CL = 3)
Burst stop
Q0
Q1
Q2
Q0
Q1
(BL = 8)
Q2
16
ALLIANCE SEMICONDUCTOR
7/5/00
Share Link: 
