ATA6612C View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
ATA6612C
Atmel Corporation
'ATA6612C' PDF : 312 Pages View PDF
5.4.5
General Purpose Register File
The register file is optimized for the AVR® enhanced RISC instruction set. In order to achieve the required performance and
flexibility, the following input/output schemes are supported by the register file:
● One 8-bit output operand and one 8-bit result input
● Two 8-bit output operands and one 8-bit result input
● Two 8-bit output operands and one 16-bit result input
● One 16-bit output operand and one 16-bit result input
Figure 5-3 shows the structure of the 32 general purpose working registers in the CPU.
Figure 5-3. AVR CPU General Purpose Working Registers
7
General
Purpose
Working
Registers
0
Address
R0
0x00
R1
0x01
R2
0x02
...
R13
0x0D
R14
0x0E
R15
0x0F
R16
0x10
R17
0x11
...
R26
0x1A
R27
0x1B
R28
0x1C
R29
0x1D
R30
0x1E
R31
0x1F
X-register Low Byte
X-register High Byte
Y-register Low Byte
Y-register High Byte
Z-register Low Byte
Z-register High Byte
Most of the instructions operating on the register file have direct access to all registers, and most of them are single cycle
instructions.
As shown in Figure 5-3, each register is also assigned a data memory address, mapping them directly into the first
32 locations of the user data space. Although not being physically implemented as SRAM locations, this memory
organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any
register in the file.
34 ATA6612C/ATA6613C [DATASHEET]
9111L–AUTO–11/14
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