ATA6612C View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
ATA6612C
Atmel Corporation
'ATA6612C' PDF : 312 Pages View PDF
5.4.5.1 The X-register, Y-register, and Z-register
The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address
pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described
in Figure 5-4.
Figure 5-4. The X-, Y-, and Z-registers
X-register
15
XH
7
0
R27 (0x1B)
XL
0
7
0
R26 (0x1A)
Y-register
15
YH
7
0
R29 (0x1D)
YL
0
7
0
R28 (0x1C)
Z-register
15
ZH
7
0
R31 (0x1F)
ZL
0
7
0
R30 (0x1E)
In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and
automatic decrement (see the instruction set reference for details).
5.4.6
Stack Pointer
The stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after
interrupts and subroutine calls. The stack pointer register always points to the top of the stack. Note that the stack is
implemented as growing from higher memory locations to lower memory locations. This implies that a stack PUSH command
decreases the stack pointer.
The stack pointer points to the data SRAM Stack area where the subroutine and interrupt stacks are located. This stack
space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled.
The stack pointer must be set to point above 0x0100, preferably RAMEND. The stack pointer is decremented by one when
data is pushed onto the stack with the PUSH instruction, and it is decremented by two when the return address is pushed
onto the stack with subroutine call or interrupt. The stack pointer is incremented by one when data is popped from the stack
with the POP instruction, and it is incremented by two when data is popped from the stack with return from subroutine RET
or return from interrupt RETI.
The AVR® stack pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is
implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only
SPL is needed. In this case, the SPH register will not be present.
Bit
15
14
13
12
11
10
9
8
SP15
SP14
SP13
SP12
SP11
SP10
SP9
SP8
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
7
6
5
4
3
2
1
0
Read/Write R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND
RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND
SPH
SPL
ATA6612C/ATA6613C [DATASHEET]
35
9111L–AUTO–11/14
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