ATA6612C View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
ATA6612C
Atmel Corporation
'ATA6612C' PDF : 312 Pages View PDF
5.4.7
Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR® CPU is driven by the CPU
clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used.
Figure 5-5 shows the parallel instruction fetches and instruction executions enabled by the harvard architecture and the
fast-access register file concept. This is the basic pipelining concept to obtain up to 1MIPS per MHz with the corresponding
unique results for functions per cost, functions per clocks, and functions per power-unit.
Figure 5-5. The Parallel Instruction Fetches and Instruction Executions
T1
T2
T3
T4
clkCPU
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
Figure 5-6 shows the internal timing concept for the register file. In a single clock cycle an ALU operation using two register
operands is executed, and the result is stored back to the destination register.
Figure 5-6. Single Cycle ALU Operation
T1
T2
T3
T4
clkCPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
5.4.8
Reset and Interrupt Handling
The AVR provides several different interrupt sources. These interrupts and the separate reset vector each have a separate
program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic
one together with the global interrupt enable bit in the status register in order to enable the interrupt. Depending on the
program counter value, interrupts may be automatically disabled when boot lock bits BLB02 or BLB12 are programmed. This
feature improves software security. See Section 5.24 “Memory Programming” on page 253 for details.
The lowest addresses in the program memory space are by default defined as the reset and Interrupt vectors. The complete
list of vectors is shown in Section 5.9 “Interrupts” on page 70. The list also determines the priority levels of the different
interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the
external interrupt request 0. The interrupt vectors can be moved to the start of the boot flash section by setting the IVSEL bit
in the MCU control register (MCUCR). Refer to Section 5.9 “Interrupts” on page 70 for more information. The reset vector
can also be moved to the start of the boot flash section by programming the BOOTRST fuse (see Section 5.23 “Boot Loader
Support – Read-While-Write Self-Programming, Atmel ATA6612C and ATA6613C” on page 240).
When an interrupt occurs, the global interrupt enable I-bit is cleared and all interrupts are disabled. The user software can
write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine.
The I-bit is automatically set when a return from interrupt instruction – RETI – is executed.
36 ATA6612C/ATA6613C [DATASHEET]
9111L–AUTO–11/14
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