ATA6612C View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
ATA6612C
Atmel Corporation
'ATA6612C' PDF : 312 Pages View PDF
5.5.2.1 Data Memory Access Times
This section describes the general access timing concepts for internal memory access. The internal data SRAM access is
performed in two clkCPU cycles as described in Figure 5-10.
Figure 5-10. On-chip Data SRAM Access Cycles
T1
T2
T3
clkCPU
Address
Compute Address
Address valid
Data
WR
Write
Data
RD
Read
Memory Access Instruction
Next Instruction
5.5.3 EEPROM Data Memory
The Atmel® ATA6612C/ATA6613C contains 512 bytes of data EEPROM memory. It is organized as a separate data space,
in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The
access between the EEPROM and the CPU is described in the following, specifying the EEPROM address registers, the
EEPROM data register, and the EEPROM control register.
The section Section 5.24 “Memory Programming” on page 253 contains a detailed description on EEPROM programming in
SPI or parallel programming mode.
5.5.3.1 EEPROM Read/Write Access
The EEPROM access registers are accessible in the I/O space.
The write access time for the EEPROM is given in Table 5-3 on page 43. A self-timing function, however, lets the user
software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some
precautions must be taken. In heavily filtered power supplies, VCC is likely to rise or fall slowly on power-up/down. This
causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used.
See Section 5.5.3.5 “Preventing EEPROM Corruption” on page 44 for details on how to avoid problems in these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the
EEPROM control register for details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When the
EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed.
40 ATA6612C/ATA6613C [DATASHEET]
9111L–AUTO–11/14
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