ATSAMA5D41A-CU View Datasheet(PDF) - Atmel Corporation
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MFG CO.
'ATSAMA5D41A-CU' PDF : 1808 Pages View PDF
14. AXI Matrix (AXIMX)
14.1
Description
The AXI Matrix comprises the embedded Advanced Extensible Interface (AXI) bus protocol which supports
separate address/control and data phases, unaligned data transfers using byte strobes, burst-based transactions
with only start address issued, separate read and write data channels to enable low-cost DMA, ability to issue
multiple outstanding addresses, out-of-order transaction completion, and easy addition of register stages to
provide timing closure.
14.2
Embedded Characteristics
High performance AXI network interconnect
1 Master:
̶ Cortex A5 Core
4 Slaves:
̶ ROM
̶ PKCC RAM
̶ PKCC ROM
̶ AXI/AHB bridge to AHB Matrix
Single-cycle arbitration
Full pipelining to prevent master stalls
1 remap state
14.3 Operation
14.3.1 Remap
Remap states are managed in the AXI Matrix Remap Register (AXIMX_REMAP): AXIMX_REMAP.REMAP0
(register bit 0) is used to remap RAM @ addr 0x00000000.
Refer to Section 14.4 “AXI Matrix (AXIMX) User Interface”.
The number of remap states can be defined using eight bits of the AXIMX_REMAP register, and a bit in
AXIMX_REMAP controls each remap state.
Each remap state can be used to control the address decoding for one or more slave interfaces. If a slave interface
is affected by two remap states that are both asserted, the remap state with the lowest remap bit number takes
precedence.
Each slave interface can be configured independently so that a remap state can perform different functions for
different masters.
A remap state can:
Alias a memory region into two different address ranges
Move an address region
Remove an address region
Because of the nature of the distributed register subsystem, the masters receive the updated remap bit states in
sequence, and not simultaneously.
A slave interface does not update to the latest remap bit setting until:
The address completion handshake accepts any transaction that is pending
Any current lock sequence completes
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SAMA5D4 Series [DATASHEET]
Atmel-11238C-ATARM-SAMA5D4-Datasheet_12-Jul-16
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