ATSAMA5D41A-CU View Datasheet(PDF) - Atmel Corporation
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MFG CO.
'ATSAMA5D41A-CU' PDF : 1808 Pages View PDF
15. Matrix (H64MX/H32MX)
15.1
Description
In order to reduce power consumption without loss in performance, the system embeds three matrixes: one based
on AXI protocol (AXIMX) and two based on AHB protocol (H64MX and H32MX). The description of the 64-bit AHB
Matrix (H64MX) and the 32-bit AHB Matrix (H32MX) implementation follows.
Refer to description of product AXIMX for complete information on the AXI Matrix.
Each AHB Matrix implements a multi-layer AHB, based on the AHB-Lite protocol, which enables parallel access
paths between multiple AHB masters and slaves in a system, thus increasing the overall bandwidth. The normal
latency to connect a master to a slave is one cycle except for the default master of the accessed slave which is
connected directly (zero cycle latency).
Note: When a master and a slave are on different bus matrixes (AXIMX, H64MX, or H32MX), both matrixes (H64MX and
H32MX) and the bridge between the bus matrixes must be configured accordingly.
15.2
Embedded Characteristics
32-bit or 64-bit data bus
MATRIX0—a 64-bit AHB matrix (H64MX) providing 10 masters for 13 slaves
MATRIX1—a 32-bit AHB matrix (H32MX) providing 7 masters for 7 slaves
One address decoder for each master
Support for long bursts of 32, 64, 128 and up to the 256-beat word burst AHB limit
Enhanced programmable mixed arbitration for each slave:
̶ Round-robin
̶ Fixed priority
̶ Latency quality of service
Programmable default master for each slave:
̶ No default master
̶ Last accessed default master
̶ Fixed default master
Deterministic maximum access latency for masters
Zero or one cycle arbitration latency for the first access of a burst
Bus lock forwarding to slaves
Master number forwarding to slaves
One special function register for each slave (not dedicated)
Register write protection
ARM TrustZone technology
15.3 MATRIX0 (H64MX)
15.3.1 Matrix Masters
The H64MX manages 10 masters, which means that each master can perform an access concurrently with others,
to an available slave.
This matrix operates at MCK.
Each master has its own decoder, which is defined specifically for each master. In order to simplify the addressing,
all the masters have the same decodings.
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SAMA5D4 Series [DATASHEET]
Atmel-11238C-ATARM-SAMA5D4-Datasheet_12-Jul-16
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