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ATSAMA5D41A-CU View Datasheet(PDF) - Atmel Corporation

Part Name
Description
MFG CO.
ATSAMA5D41A-CU
Atmel
Atmel Corporation Atmel
'ATSAMA5D41A-CU' PDF : 1808 Pages View PDF
Table 15-6. Master to Slave Access on H32MX (Continued)
0 (through Bridge from H64MX)
XDMAC0
XDMAC1
Slave
Core IF0 IF1 IF0 IF1
UDPHS RAM
X
X
5 UHP OHCI Register X
X
UHP EHCI Register X
X
6 SMD
X
X
Master
1
2
UHPHS
EHCI
ICM
DMA
3
UHPHS
OHCI
DMA
4
UDPHS
DMA
5
GMAC
0 DMA
6
GMAC
1 DMA
15.5
Memory Mapping
The Bus Matrix provides one decoder for every AHB master interface. The decoder offers each AHB master
several memory mappings. Each memory area may be assigned to several slaves. Booting at the same address
while using different AHB slaves (i.e., external RAM, internal ROM or internal Flash, etc.) becomes possible.
15.6
Special Bus Granting Mechanism
The Bus Matrix provides some speculative bus granting techniques in order to anticipate access requests from
masters. This mechanism reduces latency at first access of a burst, or for a single transfer, as long as the slave is
free from any other master access. It does not provide any benefit if the slave is continuously accessed by more
than one master, since arbitration is pipelined and has no negative effect on the slave bandwidth or access
latency.
This bus granting mechanism sets a different default master for every slave.
At the end of the current access, if no other request is pending, the slave remains connected to its associated
default master. A slave can be associated with three kinds of default masters:
No default master
Last access master
Fixed default master
To change from one type of default master to another, the Bus Matrix user interface provides Slave Configuration
Registers, one for every slave, which set a default master for each slave. The Slave Configuration Register
contains two fields to manage master selection: DEFMSTR_TYPE and FIXED_DEFMSTR. The 2-bit
DEFMSTR_TYPE field selects the default master type (no default, last access master, fixed default master),
whereas the 4-bit FIXED_DEFMSTR field selects a fixed default master provided that DEFMSTR_TYPE is set to
fixed default master. Refer to Section 15.13.2 “Bus Matrix Slave Configuration Registers”.
15.7
No Default Master
After the end of the current access, if no other request is pending, the slave is disconnected from all masters.
This configuration incurs one latency clock cycle for the first access of a burst after bus Idle. Arbitration without
default master may be used for masters that perform significant bursts or several transfers with no Idle in between,
or if the slave bus bandwidth is widely used by one or more masters.
This configuration provides no benefit on access latency or bandwidth when reaching maximum slave bus
throughput regardless of the number of requesting masters.
130
SAMA5D4 Series [DATASHEET]
Atmel-11238C-ATARM-SAMA5D4-Datasheet_12-Jul-16
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