ATSAMA5D41A-CU View Datasheet(PDF) - Atmel Corporation
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MFG CO.
'ATSAMA5D41A-CU' PDF : 1808 Pages View PDF
Table 15-3. Master to Slave Access on H64MX
0
Slave
Bridge
from
AXIMX
(Core)
0
Bridge from H64MX
to AXIMX
1
H64MX Peripheral
Bridge
X
2 VDEC
X
3 DDR2 port0 - AESB
X
4 DDR2 port1
X
5 DDR2 port2
6 DDR2 port3
7 DDR2 port4
8 DDR2 port5
9 DDR2 port6
10 DDR2 port7
11 Internal SRAM
X
12
Bridge from H64MX
to H32MX
X
1
2
XDMAC0
IF0
IF1
X
X
X
X
X
X
X
X
Master
3
4
5
6
XDMAC1
IF0
IF1
LCDC DMA
7
8
9
VDEC
DMA
ISI
DMA
Bridge
from
H32MX
X
X
X
X
X
X
X
X
X
X
X
X
15.4 MATRIX1 (H32MX)
15.4.1 Matrix Masters
The H32MX manages seven masters, which means that each master can perform an access concurrently with
others, to an available slave.
This matrix can operate at MCK if MCK is lower than 90 MHz, or at MCK/2 if MCK is higher than 90 MHz. Refer to
Section 26. “Power Management Controller (PMC)” for more details.
Each master has its own decoder, which is defined specifically for each master. In order to simplify the addressing,
all the masters have the same decodings.
Table 15-4. List of H32MX Masters
Master No.
Name
0
Bridge from H64MX to H32MX
1
Integrity Check Monitor (ICM)
2
UHP EHCI DMA
3
UHP OHCI DMA
128
SAMA5D4 Series [DATASHEET]
Atmel-11238C-ATARM-SAMA5D4-Datasheet_12-Jul-16
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