CL-PD6833-VC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PD6833-VC-A' PDF : 216 Pages View PDF
CL-PD6833
PCI-to-CardBus Host Adapter
The CL-PD6833 supports four interrupt signalling modes: PCI Interrupt Signalling mode, PC/PCI
Interrupt Signalling mode, External-Hardware Interrupt Signalling mode, and the PCI/Way serial
format.
When configured for External-Hardware Interrupt Signalling, pins 205 and 206 are used as the
ISLD and ISDAT signals to the external CL-PD6701 that provides eight parallel IRQ lines, pin 203
is INTA#, and pin 204 is INTB#/RI_OUT*. Refer to the application note “Interrupt Signalling Modes
for the CL-PD6730 and CL-PD6832” (AN-PD8).
When configured for the PCI/Way Interrupt Signalling mode, pin 205 works as the IRQSER
bidirectional interrupt line. Pin 203 works as INTA# and pin 204 works as INTB#/RI_OUT*. Pin 206
is not used. This is the only mode in which pin 203 works as an LED indicator for socket 0 and pin
205 works as a LED indicator for socket 1. Refer to the Misc. Control 5 register at Extended index
30h (memory offset 930h).
Bit 2 — Socket Power-Control Interface Signalling Mode
0
TI’s TPS2206 Serial Signalling mode (uses 3 pins, supports two sockets) or CL-PD6701 Serial
Signalling mode (currently uses TI’s TPS2206 serial protocol)
1
System Management Bus Signalling mode (uses 2 pins, supports two sockets)
When this bit is ‘0’, the TI’s TPS2206 serial interface protocol is enabled. This interface uses three
pins: SCLK, SDATA, and SLATCH. SCLK is the reference clock to the CL-PD6833. The power
control data is sent to TI’s TPS2206 over the SDATA pin and latch signal over the SLATCH pin.
When this bit is ‘1’, the Intel SMBus protocol is supported. This interface uses two pins, namely
SMBDATA and SMBCLK. The reference clock of 32 kHz is fed through the SCLK pin and is
required during suspend (both hardware and software). The power control data is sent serially
over SMBDATA (bidirectional) and clock over SMBCLK. This interface is used by MAX1601 dual-
socket power control chip (serial version) when bit 5 of this register is ‘0’. When bit 5 is ‘1’, the new
SMBus protocol is used and status read back is available.
Bit 3 — Reserved
This bit is ‘0’ if the last PCI_RST was during power-up, and ‘1’ if the last PCI_RST was a bus
segment reset with power-on.
Bit 4 — Hardware Suspend Enable
0
Normal operation
1
Device goes into Hardware Suspend if the SUSPEND# pin (133) is low.
Bits 6:5 — Reserved
Bit 7 — Multimedia ARM
0
Multimedia ARM disabled. ZV Port pins (connected to VGA ZV Port) are high-impedance.
1
Multimedia ARM enabled. ZV Port pins (connected to VGA ZV Port) are enabled.
No multimedia operation can occur without setting this bit to ‘1’; the bit provides an overriding
control mechanism. The Multimedia Arm bit ensures that multimedia operation is not inadvertently
set by software or point enablers.
This bit also controls the output drivers of the ZV Port. See the Multimedia Enable bit 0 (in
Section 11.1 on page 132). This bit must be set to ‘0’ with bit 0 of index 16h.
152
EXTENSION REGISTERS
ADVANCE DATA BOOK v0.3
June 1998
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