CL-PD6833-VC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PD6833-VC-A' PDF : 216 Pages View PDF
CL-PD6833
PCI-to-CardBus Host Adapter
11.8.8 Extension Card Status Change
Register Name: Extension Card Status Change
I/O Index: 2Fh Extended Index: 2Eh
Memory Offset: 92Eh
Bit 7
Bit 6
Bit 5
Bit 4
Reserved
R:0
R:0
R:0
R:0
Register Per: socket
Register Compatibility Type: ext.
Bit 3
(Latched)
Card Detect
Change
R/C:0
Bit 2
(Latched)
Ready
Change
R/C:0
Bit 1
(Latched)
Battery
Warning
Change
R/C:0
Bit 0
(Latched)
Battery Dead
or Status
Change
R/C:0
This register indicates the source of a management interrupt generated by the CL-PD6833.
NOTE: The corresponding bit in the Management Interrupt Configuration register must be set to ‘1’ to enable
each specific status change detection. This register can only be cleared after accessing register 804h, and
writing a ‘1’ to the corresponding bit in register 92Eh.
Bit 0 — Battery Dead Or Status Change
A transition (from high to low in Memory Card Interface mode or either high to low or low to high in
0
I/O Card Interface mode) on the BVD1/STSCHG#/RI# pin has not occurred since this register was
last read.
1
A transition on the BVD1/STSCHG#/RI# pin has occurred.
In Memory Card Interface mode, this bit is set to ‘1’ when the BVD1/STSCHG#/RI# pin (see
page 20) changes from high to low, indicating a battery dead condition. In I/O Card Interface
mode, this bit is set to ‘1’ when the BVD1/STSCHG#/RI# pin changes from either high to low or
low to high. In I/O Card Interface mode, the function of this bit is not affected by bit 7 of the
Interrupt and General Control register. This bit is reset to a ‘0’ if the Card Status register is first
cleared and then a ‘1’ is written to this bit.
Bit 1 — Battery Warning Change
0
A transition (from high to low) on the BVD2/SPKR#/LED# pin has not occurred since this register
was last read.
1
A transition on the BVD2/SPKR#/LED# pin has occurred.
In Memory Card Interface mode, this bit is set to ‘1’ when the BVD2/SPKR#/LED# pin changes
from high to low, indicating a battery warning. This bit is not valid in I/O Card Interface mode. This
bit is reset to a ‘0’ if the Card Status register is first cleared and then a ‘1’ is written to this bit.
Bit 2 — Ready Change
0
A transition on the RDY/IREQ# pin has not occurred since this register was last read.
1
A transition on the RDY/IREQ# pin has occurred.
This bit is ‘1’ when a change has occurred on the RDY/IREQ# pin. This bit is reset to a ‘0’ if the
Card Status register is first cleared and then a ‘1’ is written to this bit.
156
EXTENSION REGISTERS
ADVANCE DATA BOOK v0.3
June 1998
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