CL-PD6833-VC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PD6833-VC-A' PDF : 216 Pages View PDF
CL-PD6833
PCI-to-CardBus Host Adapter
Bit 3 — Card Detect Change
0
A transition on neither the CD1# nor the CD2# pin has occurred since this register was last read.
1
A transition on either the CD1# or the CD2# pin or both has occurred.
This bit is set to ‘1’ when a change has occurred on the CD1# or CD2# pin. This bit is reset to a
‘0’ if the Card Status register is first cleared and then a ‘1’ is written to this bit.
Bits 7:4 — Reserved
11.8.9 Misc Control 4
Register Name: Misc Control 4
I/O Index: 2Fh Extended Index: 2Fh
Memory Offset: 92Fh
Register Per: socket
Register Compatibility Type: ext.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Slot Active Socket Clock Divide Control
R:0
R:0
R:0
R:0
R:0
R:0
R/W:00
Bits 1:0 — Socket Clock Divide Control
These bits control the clock rate to the sockets and are a binary divide of the PCI input clock.
Bit 2 — Slot Active
This bit is reset to ‘0’ by RST# and by any read of this register. When the PC Card is accessed for
write or read, this bit is set. This bit can be used to monitor the traffic flow of a card. By reading
this bit during a periodic interrupt, a profile of the card activity can be established for power
management.
Bits 7:3 — Reserved
June 1998
ADVANCE DATA BOOK v0.3
EXTENSION REGISTERS
157
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