CL-PD6833-VC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PD6833-VC-A' PDF : 216 Pages View PDF
CL-PD6833
PCI-to-CardBus Host Adapter
11.8.6 Gen Map 0–6 Extra Control (I/O)
Register Name: Gen Map 0–6 Extra Control (I/O)
I/O Index: 2Fh Extended Index: 27h–2Dh
Memory Offset: 927h–92Dh
Bit 7
Bit 6
Bit 5
Bit 4
Reserved
R:0000
Bit 3
Extra
Timing
Register
Select
R/W:0
Register Per: socket
Register Compatibility Type: ext.
Bit 2
Reserved
R/W:0
Bit 1
Bit 0
Extra
Extra
Auto-Size I/O I/O Window
Window
Size
R/W:0
R/W:0
Bit 0 — Extra I/O Window Size
0
8-bit data path to Gen Map I/O Window.
1
16-bit data path to Gen Map I/O Window.
When bit 1 of this register is ‘0’, this bit determines the width of the data path for Gen Map I/O
Window accesses to the card. When bit 1 is ‘1’, this bit is ignored.
Bit 1 — Extra Auto-Size I/O Window
0
Gen Map I/O Window Size (see bit 0 of this register) determines the data path for Gen Map I/O
Window accesses.
1
The data path to Gen Map I/O Window is determined by the IOIS16# level returned by the card.
This bit determines the width of the data path for Gen Map I/O Window accesses to the card. Note
that when this bit is ‘1’, the IOIS16# signal determines the width of the data path to the card.
Bit 2 — Reserved
Bit 3 — Extra Timing Register Select
0
Accesses made with timing specified in Timer Set 0 registers.
1
Accesses made with timing specified in Timer Set 1 registers.
This bit determines the access timing specification for Gen Map I/O Window.
Bits 7:4 — Reserved
154
EXTENSION REGISTERS
ADVANCE DATA BOOK v0.3
June 1998
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