DPL4519 View Datasheet(PDF) - Unspecified
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MFG CO.
'DPL4519' PDF : 64 Pages View PDF
DPL 4519G
PRELIMINARY DATA SHEET
2.7.2. Stand-by Mode
If the DPL 4519G is switched off by first pulling
STANDBYQ low and then (after >1 µs delay) switching
off DVSUP and AVSUP, but keeping AHVSUP (‘Stand-
by’-mode), the SCART switches maintain their posi-
tion and function. This allows the copying from
selected SCART-inputs to SCART-outputs in the TV
set’s stand-by mode.
In case of power on or starting from stand-by (see
details on the power-up sequence in Fig. 4–19 on
page 52), all internal registers except the ACB register
(page 30) are reset to the default configuration (see
Table 3–5 on page 17). The reset position of the ACB
register becomes active after the first I2C transmission
into the Baseband Processing part (subaddress
12hex). By transmitting the ACB register first, the reset
state can be redefined.
2.8. I2S Bus Interfaces
The DPL 4519G has two kinds of interfaces: synchron
master/slave input/output interfaces running on 48 kHz
and an asynchron slave interface.
The interfaces accept a variety of formats with different
sample width, bit-orientation, and wordstrobe timing.
All I2S options are set by means of the MODUS or
I2S_CONFIG register.
2.8.1. Synchronous I2S-Interface(s)
The synchronous I2S bus interface consists of the
pins:
– I2S_DA_IN1, I2S_DA_IN2/3 (I2S_DA_IN2 in
PQFP80 package):
I2S serial data input, 16, 18...32 bits per sample.
– I2S_DA_OUT:
I2S serial data output, 16, 18...32 bits per sample.
– I2S_CL:
I2S serial clock.
– I2S_WS:
I2S word strobe signal defines the left and right
sample.
If the DPL 4519G serves as the master on the I2S
interface, the clock and word strobe lines are driven by
the DPL 4519G. In this mode, only 16, 32 bits per
sample can be selected. In slave mode, these lines are
input to the DPL 4519G and the DPL 4519G clock is
synchronized to 384 times the I2S_WS rate (48 kHz).
An I2S timing diagram is shown in Fig. 4–21 on
page 55.
2.8.2. Asynchronous I2S-Interface
The asynchronous I2S slave interface allows the
reception of digital audio signals with arbitrary sample
rates from 5 to 50 kHz. The synchronization is per-
formed by means of an adaptive sample rate con-
verter. No oversampling clock is required.
The following pins are used for the asynchronous I2S
bus interface (serve only as input):
– I2S_WS3
– I2S_CL3
– I2S_DA_IN2/3 (I2S_DA_IN3 in PQFP80 package).
The interface accepts I2S-input streams with MSB first
and with sample widths of 16,18...32 bits. With left/
right alignment and wordstrobe timing polarity, there
are additional parameters available for the adaption to
a variety of formats in the I2S CONFIGURATION reg-
ister.
2.8.3. Multichannel I2S-Output
Bit[0:1] of the I2S CONFIGURATION register (see
page 20) switches the output to 8 channel multichan-
nel output mode. The bit resolution per channel is 32
bit in master mode. While the first two channels can be
selected on the source select matrix, channels 3-8 are
always connected to the I2S_3 input channels 3-8.
Both, master and slave mode is possible, as long as as
the wordstrobe has only one positive edge per frame in
slave mode.
2.8.4. Asynchronous Multichannel I2S-Input
The DPL 4519G supports two kinds of asynchronous
multichannel input:
– the asynchronous I2S_3 interface can be switched
to multichannel mode (bit [8] of the I2S CONFIGU-
RATION register is set to 1. The number of chan-
nels must be even and less or equal eight.
– All I2S input lines (I2S_DA_IN1, I2S_DA_IN2 and
I2S_DA_IN3 in PQFP80 package) can be switched
to asynchronous two channel mode (bit[2] set to 1 in
the I2S CONFIGURATION register). The common
clock is I2S_WS3 and I2S_CL3. No synchronous
I2S interfaces are available in this mode.
12
Micronas
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