DPL4519 View Datasheet(PDF) - Unspecified
Part Name
Description
MFG CO.
'DPL4519' PDF : 64 Pages View PDF
DPL 4519G
PRELIMINARY DATA SHEET
Table 3–7: Write Registers on I2C Subaddress 10hex, continued
Register Function
Address
I2S CONFIGURATION
00 40hex
I2S CONFIGURATION Register
I2S31)
bit[11]
bit[10]
bit[9]
bit[8]
bit[7:4]
bit[3]
I2S data alignment (must be 0 if bit[2] = 1)
0/1
left/right aligned
wordstrobe polarity (must be 0 if bit[2] = 1)
1
0 = right, 1 = left
0
1 = right, 0 = left
wordstrobe alignment (asynchronous I2S_3)
0
WS changes at data word boundary
1
WS changes one clock cycle in advance
Sample Mode
0/1
Two/Multi sample
Word length of each data packet = (n−2)/2
bit[3]=0, bit[8]=1 (multi-sample input mode)
0111
16 bit
1000
18 bit
...
1111
32 bit
bit[3]=0, bit[8]=0 (two-sample input mode)
xxxx
16...32 bit, 18-bit valid
bit[3]=1, bit[8]=1 (multi-sample output mode)
1111
32 bit
bit[3]=1, bit[8]=0 (two-sample output mode)
0111
16 bit
1111
32 bit
I2S3 Mode
1
output (I2S3 CL/WS active)
0
input (I2S3 CL/WS tristate)
I2S1/2/3
bit[2]
I2S1/2/3 Timing
1
I2S3 timing for all I2S inputs (1/2/3)
0
default mode
I2S Out
bit[1:0]
I2S_CL frequency and I2S_DA_OUT sample length
00
2 * 16 bit (1.536 MHz Clk)
01
2 * 32 bit (3.072 MHz Clk)
10
8 * 32 bit (12.288 MHz Clk)
1) I2S_CL3 frequency depends on bit[8] and bits[7:4] as follows:
[8] = 0, [7:4] = 0111
f = fs*(2*16)
[8] = 0, [7:4] = else
f = fs*(2*32)
[8] = 1
f = fs*(8*32)
Name
I2S_CONFIG
I2S3_ALIGN
I2S3_WS_POL
I2S3_WS_MODE
I2S3_MSAMP
I2S3_MBIT
I2S3_MODE
I2S_TIMING
20
Micronas
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