DPL4519 View Datasheet(PDF) - Unspecified
Part Name
Description
MFG CO.
'DPL4519' PDF : 64 Pages View PDF
PRELIMINARY DATA SHEET
2.9. Digital Control I/O Pins
The static level of the digital input/output pins
D_CTR_I/O_0/1 is switchable between HIGH and
LOW via the I2C-bus by means of the ACB register
(see page 30). This enables the controlling of external
hardware switches or other devices via I2C-bus.
The Modus Register can set the digital input/output
pins to high impedance (see page 19). So the pins can
be used as input. The current state can be read out of
the STATUS register (see page page 21).
2.10. Clock PLL Oscillator and
Crystal Specifications
The DPL 4519G derives all internal system clocks
from the 18.432 MHz oscillator. In I2S-slave mode of
the synchronous interface, the clock is phase-locked to
the corresponding source.
For proper performance, the DPL clock oscillator
requires a 18.432-MHz crystal. Note that for the
phase-locked modes (I2S-slave), crystals with tighter
tolerance are required. The asynchronous I2S3 slave
interface uses a different locking mechanism and does
not require tighter crystal tolerances.
DPL 4519G
Micronas
13
Share Link: 
