DPL4519 View Datasheet(PDF) - Unspecified
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Description
MFG CO.
'DPL4519' PDF : 64 Pages View PDF
DPL 4519G
PRELIMINARY DATA SHEET
3. Control Interface
3.1. I2C Bus Interface
3.1.1. Device and Subaddresses
The DPL 4519G is controlled via the I2C bus slave
interface.
The IC is selected by transmitting one of the
DPL 4519G device addresses. In order to allow up to
three DPL or MSP ICs to be connected to a single bus,
an address select pin (ADR_SEL) has been imple-
mented. With ADR_SEL pulled to high, low, or left
open, the DPL 4519G responds to different device
addresses. A device address pair is defined as a write
address and a read address (see Table 3–1).
Writing is done by sending the device write address,
followed by the subaddress byte, two address bytes,
and two data bytes. Reading is done by sending the
write device address, followed by the subaddress byte
and two address bytes. Without sending a stop condi-
tion, reading of the addressed data is completed by
sending the device read address and reading two
bytes of data. Refer to Section 3.1.4. for the I2C bus
protocol and to Section 3.4. “Programming Tips” on
page 34 for proposals of DPL 4519G I2C telegrams.
See Table 3–2 for a list of available subaddresses.
Besides the possibility of hardware reset, the DPL can
also be reset by means of the RESET bit in the CON-
TROL register by the controller via I2C bus.
Due to the internal architecture of the DPL 4519G, the
IC cannot react immediately to an I2C request. The
typical response time is about 0.3 ms. If the DPL can-
not accept another complete byte of data until it has
performed some other function (for example, servicing
an internal interrupt), it will hold the clock line I2C_CL
LOW to force the transmitter into a wait state. The
positions within a transmission where this may happen
are indicated by “Wait” in Section 3.1.4. The maximum
wait period of the DPL during normal operation mode
is less than 1 ms.
3.1.2. Internal Hardware Error Handling
In case of any internal hardware error (e.g. interruption
of the power supply of the DPL), the DPL’s wait period
is extended to 1.8 ms. After this time period elapses,
the DPL releases data and clock lines.
Indicating and solving the error status:
To indicate the error status, the remaining acknowl-
edge bits of the actual I2C-protocol will be left high.
Additionally, bit[14] of CONTROL is set to one. The
DPL can then be reset via the I2C bus by transmitting
the reset condition to CONTROL.
Indication of reset:
Any reset, even caused by an unstable reset line etc.,
is indicated in bit[15] of CONTROL.
A general timing diagram of the I2C bus is shown in
Fig. 4–21 on page 55.
Table 3–1: I2C Bus Device Addresses
ADR_SEL
Mode
DPL device address
Low
(connected to DVSS)
Write
Read
80hex
81hex
High
(connected to DVSUP)
Write
Read
84hex
85hex
Left Open
Write
88hex
Read
89hex
Table 3–2: I2C Bus Subaddresses
Name
CONTROL
Binary Value
0000 0000
WR_DEM
RD_DEM
WR_DSP
RD_DSP
0001 0000
0001 0001
0001 0010
0001 0011
Hex Value
00
10
11
12
13
Mode
Read/Write
Write
Write
Write
Write
Function
Write: Software reset of DPL (see Table 3–3)
Read: Hardware error status of DPL
write address demodulator
read address demodulator
write address DSP
read address DSP
14
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