DPL4519 View Datasheet(PDF) - Unspecified
Part Name
Description
MFG CO.
'DPL4519' PDF : 64 Pages View PDF
PRELIMINARY DATA SHEET
DPL 4519G
3.3.2. Description of User Registers
3.3.2.1. Write Registers on I2C Subaddress 10hex
Table 3–7: Write Registers on I2C Subaddress 10hex
Register
Address
MODUS
00 30hex
Function
MODUS Register
bit[15:8] 0
bit[7]
0/1
bit[6]
0
1
bit[5]
0/1
bit[4]
0/1
bit[3]
0
1
bit[2:0] 0
undefined, must be 0
active/tristate state of audio clock output pin
AUD_CL_OUT
word strobe alignment (synchronous I2S)
WS changes at data word boundary
WS changes one clock cycle in advance
master/slave mode of I2S interface
active/tristate state of I2S output pins
state of digital output pins D_CTR_I/O_0 and _1
active: D_CTR_I/O_0 and _1 are output pins
(can be set by means of the ACB register)
tristate: D_CTR_I/O_0 and _1 are input pins
(level can be read out of STATUS[4,3])
undefined, must be 0
Name
MODUS
Micronas
19
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