DPL4519 View Datasheet(PDF) - Unspecified

Part Name

Description

MFG CO.

DPL4519

Sound Processor for Digital and Analog Surround Systems

Unspecified 

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DPL 4519G

PRELIMINARY DATA SHEET

I2C_DA

1

0

S

P

I2C_CL

Fig. 3–1: I2C bus protocol (MSB first; data must be stable while clock is high)

3.1.5. Proposals for General DPL 4519G

I2C Telegrams

3.1.5.1. Symbols

daw write device address (80hex, 84hex or 88hex)

dar read device address (81hex, 85hex or 89hex)

<

Start Condition

>

Stop Condition

aa Address Byte

dd Data Byte

3.1.5.2. Write Telegrams

<daw 00 d0 00>

<daw 10 aa aa dd dd>

<daw 12 aa aa dd dd>

write to CONTROL register

write data into demodulator

write data into DSP

3.1.5.3. Read Telegrams

<daw 00 <dar dd dd>

read data from

CONTROL register

<daw 11 aa aa <dar dd dd> read data from demodulator

<daw 13 aa aa <dar dd dd> read data from DSP

3.1.5.4. Examples

<80 00 80 00>

<80 00 00 00>

<80 12 00 08 08 20>

<80 12 00 00 73 00>

RESET DPL statically

Clear RESET

Set Main channel

source to I2S3 - L/R

Set Main volume to 0 dB

More examples of typical application protocols are

listed in Section 3.4. “Programming Tips” on page 34.

3.2. Start-Up Sequence:

Power-Up and I2C Controlling

After POWER ON or RESET (see Fig. 4–21), the IC is

in an inactive state. All registers are in the reset posi-

tion, the analog outputs are muted. The controller has

to initialize all registers for which a non-default setting

is necessary.

3.3. DPL 4519G Programming Interface

3.3.1. User Registers Overview

The DPL 4519G is controlled by means of user regis-

ters. The complete list of all user registers is given in

the following tables. The registers are partitioned into

two sections:

1. Subaddress 10hex for writing, 11hex for reading and

2. Subaddress 12hex for writing, 13hex for reading.

Write and read registers are 16-bit wide, whereby the

MSB is denoted bit[15]. Transmissions via I2C bus

have to take place in 16-bit words (two byte transfers,

with the most significant byte transferred first). All write

registers, except MODUS and I2S CONFIGURATION,

are readable.

Unused parts of the 16-bit write registers must be zero.

Addresses not given in this table must not be

accessed.

16

Micronas

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