DPL4519 View Datasheet(PDF) - Unspecified
Part Name
Description
MFG CO.
'DPL4519' PDF : 64 Pages View PDF
PRELIMINARY DATA SHEET
DPL 4519G
3.1.3. Description of CONTROL Register
Table 3–3: CONTROL as a Write Register
Name
Subaddress
CONTROL 00 hex
Bit[15] (MSB)
1 : RESET
0 : normal
Bits[14:0]
0
Table 3–4: CONTROL as a Read Register (only DPL 4519G-versions from A2 on)
Name
Subaddress Bit[15] (MSB)
Bit[14]
Bits[13:0]
CONTROL 00 hex
Reset status after last reading of CONTROL:
0 : no reset occured
1 : reset occured
Internal hardware status:
0 : no error occured
1 : internal error occured
not of interest
Reading of CONTROL will reset the bits[15,14] of CONTROL. After Power-on, bit[15] of CONTROL will be set; it must be
read once to be resetted.
3.1.4. Protocol Description
Write to DSP
S write Wait ACK sub-addr ACK addr-byte ACK addr-byte ACK data-byte- ACK data-byte ACK P
device
high
low
high
low
address
Read from DSP
S write Wait ACK sub-addr ACK addr-byte ACK addr-byte ACK S read Wait ACK data-byte- ACK data-byte NAK P
device
high
low
device
high
low
address
address
Write to Control
S write Wait ACK sub-addr ACK data-byte ACK data-byte ACK P
device
high
low
address
Read from Control
S write Wait ACK
device
address
00hex
ACK S read Wait ACK data-byte- ACK data-byte NAK P
device
high
low
address
Note: S =
P=
ACK =
NAK =
Wait =
I2C-Bus Start Condition from master
I2C-Bus Stop Condition from master
Acknowledge-Bit: LOW on I2C_DA from slave (= DPL, light gray) or master (= controller dark gray)
Not Acknowledge-Bit: HIGH on I2C_DA from master (dark gray) to indicate ‘End of Read’
or from DPL indicating internal error state
I2C-Clock line is held low, while the DPL is processing the I2C command.
This waiting time is max. 1 ms
Micronas
15
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