DSM2180F3 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
DSM2180F3
STMicroelectronics
'DSM2180F3' PDF : 63 Pages View PDF
DSM2180F3
DSM Security Bit
Figure 12. Page Register
A programmable security bit in the DSM protects
its contents from unauthorized viewing and copy-
ing. When set, the security bit will block access of
programming devices (JTAG or others) to the
DSM Flash memory and PLD configuration. The
only way to defeat the security bit is to erase the
entire DSM device, after which the device is blank
and may be used again. The DSP will always have
access to Flash memory contents through the 8-bit
data port even while the security bit is set. The
DSP can read the status of the security bit (but it
cannot change it) by reading the Device Security
register in the csiop block as defined in Table 8.
RESET
D0
Q0
D1
Q1
D0-D7 D2
Q2
D3
Q3
D4
Q4
D5
Q5
D6
Q6
R/W
D7
Q7
PAGE
REGISTER
PGR0
PGR1
PGR2
PGR3
PGR4
PGR5
PGR6
PGR7
DPLD
AND
CPLD
PLD
INTERNAL
SELECTS
AND LOGIC
Reset Flash
PLDs
The Reset Flash instruction sequence resets the The PLDs bring programmable logic to the device.
internal memory logic state machine and puts After specifying the logic for the PLDs using PSD-
Flash memory into Read Array mode. It consists of soft Express, the logic is programmed into the de-
one write cycle (see Table 5). It must be executed
after:
t(s) – Reading the Flash Protection Status or Flash ID
– An Error condition has occurred (and the device
c has set the Error Flag (DQ5) bit to 1) during a
u Flash memory Program or Erase cycle.
rod The Reset Flash instruction sequence puts the
Flash memory back into normal Read Array mode.
P It may take the Flash memory up to a few millisec-
te onds to complete the Reset cycle. The Reset
le Flash instruction sequence is ignored when it is is-
sued during a Program or Bulk Erase cycle of the
o Flash memory. The Reset Flash instruction se-
bs quence aborts any on-going Sector Erase cycle,
and returns the Flash memory to the normal Read
O Array mode within a few milliseconds.
) - Page Register
t(s The 8-bit Page Register increases the addressing
capability of the DSP by a factor of up to 256. The
c contents of the register can also be read by the
u DSP. The outputs of the Page Register (PG0-
d PG7) are inputs to the DPLD decoder and can be
ro included in the Sector Select (FS0-FS7) equa-
P tions. See Figure 12.
te If memory paging is not needed, or if not all 8 page
register bits are needed for memory paging, then
le these bits may be used in the CPLD for general
o logic. The eight flip-flops in the register are con-
s nected to the internal data bus D0-D7. The DSP
bcan write to or read from the Page Register. The
OPage Register can be accessed at address loca-
vice and available upon Power-up.
The PLDs have selectable levels of performance
and power consumption.
The device contains two PLDs: the Decode PLD
(DPLD), and the Complex PLD (CPLD), as shown
in Figure 13.
Table 9. DPLD and CPLD Inputs
Input Source
Input Name
DSP Address Bus1
A15-A0
DSP Control Signals2 CNTL2-CNTL0
Reset
RST
PortB Input Macrocells PB7-PB0
PortC Input Macrocells PC7-PC0
Port D Inputs
PD2-PD0
Page Register
PG7-PG0
Macrocell AB
Feedback
MCELLAB FB7-0
Macrocell BC
Feedback
MCELLBC FB7-0
Flash memory
Program Status Bit
Ready/Busy
Number
of
Signals
16
3
1
8
8
3
8
8
8
1
tion csiop + E0h. Page Register outputs are
cleared to logic 0 at reset.
Note: 1. DSP address lines A16, A17, and others may enter the
DSM device on any pin on ports B, C, or D. See Figure 6
for recommended connections.
2. Additional DSP control signals may enter the DMS device
on any pin on Ports B, C, or D. See Figure 6 for recom-
mended connections.
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