DSM2180F3 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
DSM2180F3
STMicroelectronics
'DSM2180F3' PDF : 63 Pages View PDF
DSM2180F3
DECODE PLD (DPLD)
The DPLD, shown in Figure 14, is used for decod-
ing the address for internal and external compo-
nents. The DPLD can be used to generate the
following decode signals:
■ 8 Flash memory Sector Select (FS0-FS7)
signals with three product terms each
■ 1 internal csiop select for DSM device control
and status registers (csiop is the base address
of the block of 256 byte locations)
■ 1 JTAG Select signal (enables JTAG operations
on Port C when multiplexing JTAG signals with
general I/O signals)
■ 3 external chip select output signals for Port D
pins, each with one product term.
Figure 14. DPLD Logic Array
ct(s) I/O PORTS (PORT A,B,C)
(INPUTS)
(16)
du MCELLAB.FB [7:0] (Feedback)
(8)
ro MCELLBC.FB [7:0] (Feedback)
(8)
te P PG0-PG7
(8)
le A[15:0]
(16)
so PD[2:0]
(3)
Ob CNTRL[2:0] (Read/Write Control Signals) (3)
) - RESET
(1)
Obsolete Product(s RD_BSY
(1)
3
FS0
3
FS1
3
FS2
3
FS3
8 Flash Memory
3
Sector Selects
FS4
3
FS5
3
FS6
3
FS7
1
CSIOP
I/O Decoder
Select
1
JTAGSEL JTAG ISP
1
ECS0
1
ECS1
External Chip Selects
to PORT D
1
ECS2
AI04901
27/63
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