DSM2180F3 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
DSM2180F3
STMicroelectronics
'DSM2180F3' PDF : 63 Pages View PDF
DSM2180F3
COMPLEX PLD (CPLD)
The CPLD can be used to implement system logic
functions, such as loadable counters and shift reg-
isters, system mailboxes, handshaking protocols,
state machines, and random logic. See application
note AN1171 for details on how to specify logic us-
ing PSDsoft Express.
As shown in Figure 15, the CPLD has the following
blocks:
■ 16 Input Macrocells (IMC)
■ 16 Output Macrocells (OMC)
■ Macrocell Allocator
■ Product Term Allocator
■ AND Array capable of generating up to 130
product terms
■ Two I/O Ports.
Each of the blocks are described in the sections
that follow.
The Input Macrocells (IMC) and Output Macrocells
(OMC) are connected to the device internal data
bus and can be directly accessed by the DSP. This
enables the DSP software to load data into the
Output Macrocells (OMC) or read data from both
the Input and Output Macrocells (IMC and OMC).
This feature allows efficient implementation of sys-
tem logic and eliminates the need to connect the
data bus to the AND Array as required in most
standard PLD macro cell architectures.
Figure 15. Macrocell and I/O Port
t(s) Product Terms
from other
MacrocellS
DSP ADDRESS / DATA BUS
uc CPLD Macrocells
rod PRODUCT TERM
P ALLOCATOR
PT PRESET
MCU DATA IN
MCU LOAD
DATA
LOAD
CONTROL
te UP TO 10
le PRODUCT TERMS
so POLARITY
SELECT
Ob PT
CLOCK
- GLOBAL
) CLOCK
t(s CLOCK
SELECT
uc PT CLEAR
Macrocell
Out to
MCU
PR DI LD
D/T
Q
D/T/JK FF
SELECT
CK
CL
COMB.
/REG
SELECT
CPLD
OUTPUT
Macrocell
to
I/O Port
Alloc.
rod PT Output Enable (OE)
PMacrocell Feedback
te I/O Port Input
Obsole PT INPUT LATCH GATE/CLOCK
TO OTHER I/O PORTS
I/O PORTS
LATCHED
ADDRESS OUT
DATA
WR
DQ
MUX
CPLD OUTPUT
I/O Pin
PDR
INPUT
SELECT
DQ
DIR
WR
REG.
Input Macrocells
QD
QD
G
AI04902B
Output Macrocell (OMC). Eight of the Output The Output Macrocell (OMC) architecture is
Macrocells (OMC) are connected to Port B pins shown in Figure 17. As shown in the figure, there
and are named as McellAB0-McellAB7. The other are native product terms available from the AND
eight Macrocells are connected to Ports B or C Array, and borrowed product terms available (if
pins and are named as McellBC0-McellBC7. unused) from other Output Macrocells (OMC). The
OMCs may be used for internal feedback only polarity of the product term is controlled by the
(buried registers), or their outputs may be routed XOR gate. The Output Macrocell (OMC) can im-
to external Port pins.
plement either sequential logic, using the flip-flop
28/63
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