LH28F040SUTD-Z4 View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LH28F040SUTD-Z4' PDF : 32 Pages View PDF
4M (512K × 8) Flash Memory
POWER-UP AND RESET TIMINGS
VCC POWER UP
tELRS
BEX (E)
(NOTE)
LH28F040SUTD-Z4
tEHRS
OE (G)
WE (W)
VCC (3.5 V)
0V
tGLRS
3.3 V
3.0 V
tWLPL
tGHRS
3.3 V
ADDRESS (A)
VALID
tAVQV
DATA (Q)
NOTE: BEX means either BE0 or BE1
Figure 16. VCC Power-Up and RP » Reset Waveforms
tPHQV
VALID
3.3 V OUTPUTS
28F040SUZ4-16
SYMBOL
PARAMETER
MIN. MAX. UNITS NOTE
tWLPL WE Low to VCC at 3.0 V MIN.
5
µs
1
tAVQV Address Valid to Data Valid for VCC = 3.3 V ± 0.3 V
150
ns
2
tPHQV WE High to Data Valid for VCC = 3.3 V ± 0.3 V
500
ns
2
tELRS BE»0 and BE»1 Setup to WE Going Low
100
ns
tGLRS OE» Setup to WE Going Low
100
ns
tEHRS BE»0 and BE»1 Hold from WE Going High
100
ns
tGHRS OE» Hold from WE Going High
100
ns
NOTES:
BE »0, BE »1 and OE » must be set high once after power-up. BE »0 and BE »1 must not be set low at the same time.
1. Chip reset is enabled when the low state of all BE »0 (or BE »1), OE » and WE » exceeds 5 µs. Especially when you will
power on the chip, execute an above chip reset sequence for a protection from noise. All BE »0 (or BE »1), OE » and WE »
must not be low, except for the purpose of chip reset.
2. These values are shown for 3.3 V VCC operation. Refer to the AC Characteristics Read Only Operations also.
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