LPC1777 View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
LPC1777
NXP Semiconductors.
'LPC1777' PDF : 120 Pages View PDF
NXP Semiconductors
LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
Table 18. Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits) = 00
CL = 10 pF, Tamb = 40 C to 85 C, VDD(3V3) = 3.0 V to 3.6 V. Values guaranteed by design. tfbdly is programmable delay
value for the feedback clock that controls input data sampling; tclk0dly is programmable delay value for the EMC_CLKOUT0
output; tclk1dly is programmable delay value for the EMC_CLKOUT1 output.
Symbol
Parameter
Min
Typ
Max
Unit
Common to read and write cycles
Tcy(clk)
clock cycle time
[1] 12.5
-
-
ns
td(SV)
chip select valid delay time
[2] -
tclkndly + 4.2
tclk0dly + 6.2
ns
th(S)
chip select hold time
[2] tclkndly + 1.2
tclkndly + 1.8
-
ns
td(RASV)
row address strobe valid delay
[2] -
time
tclkndly + 4.2
tclkndly + 6.2
ns
th(RAS)
td(CASV)
row address strobe hold time
column address strobe valid
delay time
[2] tclkndly+ 1.3
[2] -
tclkndly + 1.9
-
ns
tclkndly + 4.2
tclkndly + 6.2
ns
th(CAS)
column address strobe hold
[2] tclkndly + 1.3
tclkndly + 1.9
-
ns
time
td(WV)
write valid delay time
[2] -
tclkndly + 5.2
tclkndly + 7.7
ns
th(W)
write hold time
[2] tclkndly + 1.6
tclkndly + 2.4
ns
td(AV)
address valid delay time
[2] -
tclkndly + 5.0
tclkndly + 7.4
ns
th(A)
address hold time
[2] tclkndly + 1.1
tclkndly + 1.7
-
ns
Read cycle parameters when EMC_CLKOUT0 used
tsu(D)
data input set-up time
7.1 - tfbdly
4.8 - tfbdly
-
ns
th(D)
data input hold time
-1.9 + tfbdly
-2.5 + tfbdly
-
ns
Read cycle parameters when EMC_CLKOUT1 used
tsu(D)
data input set-up time
7.1 - tfbdly + (tclk1dly 4.8 - tfbdly + (tclk1dly -
ns
- tclk0dly)
- tclk0dly)
th(D)
data input hold time
-1.9 + tfbdly -
-2.5 + tfbdly -
-
ns
(tclk1dly - tclk0dly)
(tclk1dly - tclk0dly)
Write cycle parameters
td(QV)
th(Q)
data output valid delay time
data output hold time
[2] -
[2] tclkndly 0.4
tclkndly + 5.8
tclkndly + 0.6
tclkndly + 8.7
ns
-
ns
[1] Refers to SDRAM clock signal EMC_CLKOUTn where n = 0 and 1.
[2] tclkndly represents tclk0dly when EMC_CLKOUT0 clocks SDRAM. tclkndlyrepresents tclk1dly when EMC_CLKOUT1 clocks SDRAM.
LPC178X_7X
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5.5 — 26 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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