LPC1777 View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
LPC1777
NXP Semiconductors.
'LPC1777' PDF : 120 Pages View PDF
NXP Semiconductors
LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
Table 22. Dynamic characteristics: Dynamic external memory interface programmable clock delays (CMDDLY,
FBCLKDLY, CLKOUT0DLY and CLKOUT1DLY)
Tamb = 40 C to 85 C, VDD(3V3) = 3.0 V to 3.6 V.Values guaranteed by design. tcmddly is programmable delay value for EMC
command outputs in command delayed mode; tfbdly is programmable delay value for the feedback clock that controls input
data sampling; tclk0dly is programmable delay value for the EMC_CLKOUT0 output; tclk1dly is programmable delay value for the
EMC_CLKOUT1 output.
Symbols
Parameter Five bit value for each delay in EMCDLYCTL[1] Min Typ Max Unit
tcmddly, tfbdly, tclk0dly, tclk1dly delay time
b00000
b00001
0.0 0.0 0.0
ns
0.1 0.1 0.2
ns
b00010
0.2 0.3 0.5
ns
b00011
0.3 0.4 0.7
ns
b00100
0.5 0.8 1.3
ns
b00101
0.6 0.9 1.5
ns
b00110
0.7 1.1 1.8
ns
b00111
0.8 1.2 2.0
ns
b01000
1.2 1.8 2.9
ns
b01001
1.3 1.9 3.1
ns
b01010
1.4 2.0 3.4
ns
b01011
1.5 2.1 3.6
ns
b01100
1.7 2.6 4.2
ns
b01101
1.8 2.7 4.4
ns
b01110
1.9 2.9 4.7
ns
b01111
2.0 3.0 4.9
ns
b10000
2.4 3.7 6.0
ns
b10001
2.5 3.8 6.2
ns
b10010
2.6 4.0 6.5
ns
b10011
2.7 4.1 6.7
ns
b10100
2.9 4.5 7.3
ns
b10101
3.0 4.6 7.5
ns
b10110
3.1 4.8 7.8
ns
b10111
3.2 4.9 8.0
ns
b11000
3.6 5.4 8.9
ns
b11001
3.7 5.5 9.1
ns
b11010
3.8 5.7 9.4
ns
b11011
3.9 5.8 9.6
ns
b11100
4.1 6.2 10.2 ns
b11101
4.2 6.3 10.4 ns
b11110
4.3 6.6 10.7 ns
b11111
4.4 6.7 10.9 ns
[1] The programmable delay blocks are controlled by the EMCDLYCTL register in the EMC register block. All
delay times are incremental delays for each element starting from delay block 0. See the LPC178x/7x user
manual for details.
LPC178X_7X
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5.5 — 26 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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