LPC1777 View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
LPC1777
NXP Semiconductors.
'LPC1777' PDF : 120 Pages View PDF
NXP Semiconductors
LPC178x/7x
32-bit ARM Cortex-M3 microcontroller
Table 21. Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits) = 01
CL = 30 pF, Tamb = 40 C to 85 C, VDD(3V3) = 3.0 V to 3.6 V. Values guaranteed by design. tcmddly is programmable delay
value for EMC command outputs in command delayed mode; tfbdly is programmable delay value for the feedback clock that
controls input data sampling; tclk0dly is programmable delay value for the EMC_CLKOUT0 output; tclk1dly is programmable
delay value for the EMC_CLKOUT1 output.
Symbol
Parameter
Min
Typ
Max
Unit
For RD = 1 tclk0dly = 0 and tclk1dly = 0
Common to read and write cycles
Tcy(clk)
clock cycle time
[1] 12.5
-
-
ns
td(SV)
chip select valid delay time
-
tcmddly + 6.4
tcmddly + 9.5
ns
th(S)
chip select hold time
tcmddly + 0.9
tcmddly + 1.7
-
ns
td(RASV)
row address strobe valid
-
delay time
tcmddly + 6.4
tcmddly + 9.5
ns
th(RAS)
row address strobe hold
tcmddly + 1.0
tcmddly + 1.8
-
ns
time
td(CASV)
column address strobe valid
-
delay time
tcmddly + 6.5
tcmddly + 9.6
ns
th(CAS)
column address strobe hold
tcmddly + 1.0
tcmddly + 1.8
-
ns
time
td(WV)
write valid delay time
th(W)
write hold time
td(AV)
address valid delay time
th(A)
address hold time
Read cycle parameters
-
tcmddly + 1.4
-
tcmddly + 0.8
tcmddly + 7.1
tcmddly + 2.4
tcmddly + 7.2
tcmddly + 1.5
tcmddly + 10.6
ns
-
ns
tcmddly + 10.6
ns
-
ns
tsu(D)
data input set-up time
8.3 - tfbdly
5.5 - tfbdly
-
ns
th(D)
data input hold time
-1.9 + tfbdly
-2.5 + tfbdly
-
ns
Write cycle parameters
td(QV)
th(Q)
data output valid delay time
data output hold time
-
tcmddly + 0.02
tcmddly + 7.4
tcmddly + 0.6
tcmddly + 10.8
ns
-
ns
[1] Refers to SDRAM clock signal EMC_CLKOUTn where n = 0 and 1.
LPC178X_7X
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5.5 — 26 April 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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