PH955L View Datasheet(PDF) - Philips Electronics
Part Name
Description
MFG CO.
'PH955L' PDF : 12 Pages View PDF
Philips Semiconductors
PH955L
N-channel TrenchMOS™ logic level FET
120
Pder
(%)
80
03aa16
120
Ider
(%)
80
03aa24
40
40
0
0
50
100
150
200
Tmb (°C)
Pder = P-------P----t--o---t------- × 100 %
tot(25 °C)
Fig 1. Normalized total power dissipation as a
function of mounting base temperature
103
ID
(A)
102
Limit RDSon = VDS / ID
10
1
0
0
50
100
150
200
Tmb (°C)
Ider = -I-------I--D--------- × 100 %
D(25 °C)
Fig 2. Normalized continuous drain current as a
function of mounting base temperature
003aaa777
tp = 10 µs
100 µs
1 ms
10 ms
DC
100 ms
10-1
10-1
1
10
102
VDS (V)
Tmb = 25 °C; IDM is single pulse; VGS = 10 V
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage
9397 750 14557
Product data sheet
Rev. 01 — 1 March 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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