QL5030-4TQ144C View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
QL5030-4TQ144C
QuickLogic Corporation
'QL5030-4TQ144C' PDF : 18 Pages View PDF
QL5030 QuickPCI Data Sheet
2.0 Architecture Overview
The QL5030 device in the QuickLogic QuickPCI ESP (Embedded Standard Product) family provides a
complete and customizable PCI interface solution combined with 24,000 system gates of programmable
logic. This device eliminates any need for the designer to worry about PCI bus compliance, yet allows
for the maximum 32-bit PCI bus bandwidth (132 MB/s).
The programmable logic portion of the device contains 266 QuickLogic Logic Cells, and 8 QuickLogic
Dual-Port RAM Blocks. These configurable RAM blocks can be configured in many width/depth
combinations. They can also be combined with logic cells to form FIFOs, or be initialized via Serial
EEPROM on power-up and used as ROMs. See the RAM section of this data sheet for more information.
The QL5030 device meets PCI 2.2 electrical and timing specifications and has been fully hardware-
tested. This device also supports the Win'98 and PC'98 standards. The QL5030 device features 3.3-volt
operation with multi-volt compatible I/Os. Thus it can easily operate in 3.3-volt systems and is fully
compatible with 3.3V, 5V or Universal PCI card development.
2.1 PCI Interface
The PCI target is PCI 2.2 compliant and supports 32-bit/33 MHz operation. It is capable of zero wait-
state infinite-length read and write transactions (132 MBytes/second). Transaction control is available via
the user interface as retries, wait-states, or premature transaction termination may be induced if
necessary. The PCI configuration registers are implemented in the programmable region of the device,
leaving the designer with ample flexibility to support optional features.
The QL5030 device supports maximum 32-bit PCI transfer rates, so many applications exist which are
ideally suited to the device's high performance. High-speed data communications, telecommunications,
and computing systems are just a few of the broad range of applications areas that can benefit from the
high speed PCI interface and programmable logic.
2.2 PCI Configuration Space
The QL5030 supports customization of required Configuration Registers such as Vendor ID, Device ID,
Subsystem Vendor ID, etc.. QuickLogic provides a reference Configuration Space design block.
Since the PCI Configuration Registers are implemented in the programmable region of the QL5030,
the designer can implement optional features such as multiple 32-bit Base Address Registers (BARs) and
multiple functions, as well as support the following PCI commands: I/O Read, I/O Write, Memory Read,
Memory Write, Config Read (required), Configuration Write (required), Memory Read Multiple, Memory
Read Line, and Memory Write and Invalidate. Additionally, the device supports Extended Capabilities
Registers, Expansion ROMs, power management, CompactPCI hot-plug/hot-swap, Vital Product Data,
I20, and mailbox registers.
2.3 Address and Command Decode
PCI address and command decoding is performed by logic in the programmable section of the device.
This allows support for any size of memory or I/O space for back-end logic. It also allows the user to
implement any subset of the PCI commands supported by the QL5030. QuickLogic provides a
reference Address Register/Counter and Command Decode block.
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© 2002 QuickLogic Corporation
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