QL5030-4TQ144C View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
QL5030-4TQ144C
QuickLogic Corporation
'QL5030-4TQ144C' PDF : 18 Pages View PDF
QL5030 QuickPCI Data Sheet
5.0 Internal Interface Signal Descriptions
Signals used to connect to the PCI interface in the QL5030 are described below. The direction of the
signal indicates if it is an input provided by the local interface (I) or an output provided by the PCI
interface (O).
Table 1: Internal Interface Signal Descriptions
Signal
I/O
Description
Usr_Addr_WrData[31:0]
Target address, and data from target writes. During all target accesses, the address will be presented
O on Usr_Addr_WrData[31:0] and simultaneously, Usr_Adr_Valid will be active. During target write
transactions, this port will also present write data to the PCI configuration space or user logic.
Usr_CBE[3:0]
PCI command and byte enables. During target accesses, the PCI command will be presented on
O Usr_CBE[3:0] and simultaneously, Usr_Adr_Valid will be active. During target read or write
transactions, this port will present active-low byte-enables to the PCI configuration space or user logic.
Usr_Adr_Valid
Indicates the beginning of a PCI transaction, and that a target address is valid on
Usr_Addr_WrData[31:0] and the PCI command is valid on Usr_CBE[3:0]. When this signal is active,
O
the target address must be latched and decoded to determine if this address belongs to the device's
memory space. Also, the PCI command must be decoded to determine the type of PCI transaction.
On subsequent clocks of a target access, this signal will be low, indicating that an address is NOT
present on Usr_Addr_WrData[31:0].
Usr_Adr_Inc
Indicates that the target address should be incremented, because the previous data transfer has
completed. During burst target accesses, the target address is only presented to the back-end logic
at the beginning of the transaction (when Usr_Adr_Valid is active), and must therefore be latched and
incremented (by 4) for subsequent data transfers. Note that during write transactions, Usr_Adr_Inc
O indicates valid data on Usr_Addr_WrData[31:0] that must be accepted by the back-end logic
(regardless of the state of Usr_Rdy). During read transactions, Usr_Adr_Inc will signal to the back-end
that the PCI core is ready to accept data. Usr_Adr_Inc and Usr_Rdy both active during a read
transaction signals a data transfer between the FPGA and the PCI core (and that the address counter
must be incremented).
Usr_RdDecode
This signal should be driven active when a "user read" command has been decoded from the
I Usr_CBE[3:0] bus (while Usr_Adr_Valid is active). This command may be mapped from any of the PCI
"read" commands, such as Memory Read, Memory Read Line, Memory Read Multiple, I/O Read, etc.
Usr_WrDecode
This signal should be driven active when a "user write" command has been decoded from the
I Usr_CBE[3:0] bus (while Usr_Adr_Valid is active). This command may be mapped from any of the PCI
"write" commands, such as Memory Write or I/O Write.
Usr_Select
This signal should be driven active when the address on Usr_Addr_WrData[31:0] has been decoded
and determined to be within the address space of the device. Usr_Addr_WrData[31:0] must be
I compared to each of the valid Base Address Registers in the PCI configuration space. Also, this signal
must be gated by the Memory Access Enable or I/O Access Enable registers in the PCI configuration
space (Command Register bits 1 or 0 at offset 04h).
Usr_Write
This signal will be active throughout a "user write" transaction, which has been decoded by
O
Usr_WrDecode at the beginning of the transaction. The write-enable for individual double-words of
data (on Usr_Addr_WrData[31:0]) during a user write transaction should be generated by logically
ANDing this signal with Usr_Adr_Inc.
Cfg_Write
This signal will be active throughout a configuration write transaction. The write-enable for individual
O double-words of data (on Usr_Addr_WrData[31:0]) during a configuration write transaction should be
generated by logically ANDing this signal with Usr_Adr_Inc.
Cfg_RdData[31:0]
I
Data from the PCI configuration registers, required to be presented to the PCI core during PCI
configuration reads.
Usr_RdData[31:0]
I Data from the back-end user logic, required to be presented during PCI reads.
Cfg_CmdReg8Cfg_CmdReg6 I Bits 6 and 8 from the Command Register in the PCI configuration space (offset 04h).
(Sheet 1 of 2)
QL5030 QuickPCI Data Sheet Rev C
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