QL5030 QuickPCI Data Sheet
6.0 Array of Logic Cells
A wide range of additional features complements the QL5030 device. The FPGA portion of the device
is 5-volt and 3.3-volt PCI-compliant and can perform high-speed logic functions such as 160 MHz
FIFOs. I/O pins provide individually controlled output enables, dedicated input/feedback registers, and
full JTAG capability for boundary scan and test. In addition, the QL5030 device provides the benefits of
non-volatility, high design security, immediate functionality on power-up, and a single chip solution.
The QL5030 programmable logic architecture consists of an array of user-configurable logic building
blocks, called logic cells, set beneath a grid of metal wiring channels similar to those of a gate array.
Through ViaLink® elements located at the wire intersections, the output(s) of any cell may be
programmed to connect to the input(s) of any other cell. Using the programmable logic in the QL5030,
designers can quickly and easily customize their “back-end” design for any number of applications.
QS
A1
A2
A3
A4
AZ
A5
A6
OS
OP
B1
B2
C1
OZ
C2
MP
MS
QZ
D1
D2
E1
E2
NP
NZ
NS
F1
F2
F3
F4
FZ
F5
F6
QC
QR
Figure 4: Logic Cell
QL5030 QuickPCI Data Sheet Rev C
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