QL5030-4TQ144C View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
QL5030-4TQ144C
QuickLogic Corporation
'QL5030-4TQ144C' PDF : 18 Pages View PDF
QL5030 QuickPCI Data Sheet
Signal
Cfg_PERR_Det
Cfg_SERR_Sig
Usr_TRDYN
Usr_STOPN
Usr_Devsel
Usr_Last_Cycle_D1
RdPipe_Stat[1:0]
Usr_Rdy
Usr_Stop
Table 1: Internal Interface Signal Descriptions (Continued)
I/O
Description
O
Parity error detected on the PCI bus. When this signal is active, bit 15 of the Status Register must be
set in the PCI configuration space (offset 04h).
O
System error asserted on the PCI bus. When this signal is active, the Signaled System Error bit, bit
14 of the Status Register, must be set in the PCI configuration space (offset 04h).
O Copy of the TRDYN signal as driven by the PCI target interface.
O Copy of the STOPN signal as driven by the PCI target interface.
O Inverted copy of the DEVSELN signal as driven by the PCI target interface.
O Indicates that the last transfer in a PCI transaction is occurring.
Indicates the number of dwords currently in the read pipeline ("00" = 0 elements, "01" = 1 element,
"11" = 2 elements). This value is important at the end of a transaction (i.e. when Usr_Last_Cycle_D1
O
is active) if non-prefetchable memory is being read. Non-prefetchable memory is defined as registers
or memory elements whose value changes when they are read. Examples are status registers which
are cleared when they are read, or FIFO memories, since consecutive reads from the same address
in these elements may not produce the same data values.
I
Used to delay (add wait states to) a PCI transaction when the back end needs additional time. Subject
to PCI latency restrictions.
I Used to prematurely stop a PCI target access on the next PCI clock.
(Sheet 2 of 2)
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