QL5030 QuickPCI Data Sheet
3.0 RAM Architecture Overview
The RAM modules in the programmable region can be used to create configurable 32-bit FIFOs. Each
32-bit FIFO can be independently assigned to Target address space for read pre-fetch or write posting.
Using the 8 QuickLogic RAM modules, the combinations include:
• 4 independent 64-deep FIFO (2 RAMs each),
or
• 2 independent 128-deep FIFOs (4 RAMs each),
or
• a combination of the above that requires 8 or less QuickLogic RAM Modules
Asynchronous FIFOs (with independent read and write clocks) are also supported.
Figure 2: Graphical Interface to create FIFO
QL5030 QuickPCI Data Sheet Rev C
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