QL5064-33APB484I View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
QL5064-33APB484I
QuickLogic Corporation
'QL5064-33APB484I' PDF : 37 Pages View PDF
QL5064 QuickPCI Data Sheet
13.0 Control Registers
DMA Control and QL5064 registers can be accessed from the PCI bus or the back-end Control_DATA
bus. On the PCI side, these registers are accessed off of BAR 0, with offets 0x00 to 0xFF (below 0x100).
The breakdown of this memory space can be seen in the following table.
USER Memory Map
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Master Write Address 0[63:0] (r/w)
00
Master Write Count Status0[31:0] (r only)
Master Write Transfer Count0[31:0] (r/w)
08
Master Write Address 1[63:0] (r/w)
10
Master Write Count Status1[31:0] (r only)
Master Write Transfer Count1[31:0] (r/w)
18
00 strt
32
bit
0000
Single PCI Access
cmd[3:0] byte lanes[7:0]
BAR Enable (r only)
rom 5 4 3 2 1 0 BAR5
Receive FIFO 1
tag0 Bus Request
Pipeline
Not Empty
Byte Lane[7:0]
[1:0] XMT XMT RCV RCV XMT XMT
010101
Target BAR Configuration (r only)
BAR4 BAR3 BAR2 BAR1 BAR0
Receive FIFO 0
Chip Revision ID [7:0] User ID [7:0] (r only)
Byte Lane[7:0]
(r only)
antifuse
Target FIFO
Threshold
MSB's[3:0]
Target FIFO Control -- Emptyness Threshold
0
BAR5 BAR4 BAR3 BAR2 BAR1 BAR0
Target Prefetch Cntl
BAR[5:0]
0 Target Burst Request
BAR[5:0]
20
28
I2O Interrupt Mask Bit [3]
I2O Interrupt Service Request Bit [3]
30
Reserved
38
I2O Outbound Queue Pointer
I2O Inbound Queue Pointer
40
Master Read Address 0[63:0] (r/w) / Chain Descriptor Start Address [63:0] (r/w) 48
Master Read Count Status0[31:0] (r only)
Master Read Transfer Count0[31:0] (r/w)
50
Master Read Address 1[63:0] (r/w)
58
Master Read Count Status1[31:0] (r only)
Master Read Transfer Count1[31:0] (r/w)
60
00
XMIT FIFO 1
Almost Full[5:0]
(r/w)
00
XMIT FIFO 0
Almost Full[5:0]
(r/w)
00
XMIT FIFO 1
Almost Empty[5:0]
(r/w)
00
XMIT FIFO 0
Almost Empty[5:0]
(r/w)
00
Receive FIFO1
Almost Full[5:0]
(r/w)
00
Receive FIFO0
Almost Full[5:0]
(r/w)
00
Receive FIFO1
Almost Empty[5:0]
(r/w)
00
Receive FIFO0
Almost Empty[5:0]
(r/w)
68
70 User Incoming Mail 7 User Incoming Mail 6 User Incoming Mail 5 User Incoming Mail 4 User Incoming Mail 3 User Incoming Mail 2 User Incoming Mail 1 User Incoming Mail 0
78 User Outgoing Mail 7 User Outgoing Mail 6 User Outgoing Mail 5 User Outgoing Mail 4 User Outgoing Mail 3 User Outgoing Mail 2 User Outgoing Mail 1 User Outgoing Mail 0
0000_0000
0000_0000
0000
0000_0000 0000_0000 0000_0000
I2O Interrupt
oflf ople iplf ifle
DMA Interrupt
User Outgoing MB
CE chn rcv1 rcv0 xmt1xmt0
Empty [7:0]
0000_0000 PCI Incoming MB Empty PCI Outgoing MB Empty
Interrupt Mask[7:0]
Interrupt Mask[7:0]
I2O Int Mask
oflf ople iplf ifle
DMA Interrupt Mask User Outgoing MB Empty
CE chn rcv1 rcv0 xmt1xmt0 Interrupt Mask[7:0]
Error
0
SPCI Chn rcv1 rcv0 xmt1xmt0
User region
[2:0]
user_be_req[7:0]
I2O Status
oflf ople iplf ifle
0 Chain DMA Start/Done#
Ptr
Fetch
End chn rcv1 rcv0 xmt1xmt0
User Outgoing MB
Status [7:0]
Single PCI Access Address Register[63:0] (r/w)
User Incoming MB
Full [7:0]
User Incoming MB Full
Interrupt Mask[7:0]
User Incoming MB
Status [7:0]
80
88
90
98
Single PCI Access Data Register[63:0] (r/w)
a0
Reserved
a8
Receive FIFO0[63:0] (r only)
b0
Receive FIFO1[63:0] (r only)
b8
Transmit FIFO0[63:0] (w only)
c0
0000_0000
Transmit FIFO1[63:0] (w only)
0000_00
0000 Arb DMA Arbitration Priority
Mode
[1:0] rcv1[1:0] rcv0[1:0] xmt1[1:0] xmt0[1:0]
0000 DMA 32/64#
DMA SPC
FIFO
0 Flush
DMA Cancel
000
rcv1 rcv0 xmt1xmt0
rcv1 rcv0 xmt1xmt0 xmt1xmt0 Chn rcv1 rcv0 xmt1xmt0
Reserved
c8
0 d0 BIST
Code[3:0]
BE En
[1:0]
Max
Retry
[1:0]
FIFO
Thresh
TO[1:0]
lat
en
d8
Reserved
e0
Reserved
e8
Target Control Address[63:0] (r only)
000 f0
Target Control Data[63:0] (r/w)
f8
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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12
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