QL5064-33APB484I View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
QL5064-33APB484I
QuickLogic Corporation
'QL5064-33APB484I' PDF : 37 Pages View PDF
QL5064 QuickPCI Data Sheet
17.0 PCI to Programmable Logic Interface
The QL5064 device is designed to be highly customizable. This diagram illustrates the interface signals
present between the configurable PCI core, and the programmable logic region of the QL5064 device.
Detailed descriptions of each of these interface signals follow in the next section.
AD[63:0]
C/BE[7:0]
PAR
FRAME#
TRDY#
IRDY#
STOP#
DEVSEL#
IDSEL
PERR#
SERR#
REQ#
GNT#
CLK
RST#
PAR64
REQ64#
ACK64#
INTA#
TDI
TDO
TCK
TMS
TRST#
pci_clk_2fpga
user_clk
fpga_reset
user_region[2:0]
user_stop
user_be_req[7:0]
user_rdwr
user_addr_valid
user_req
user_mult
user_addr_output[32:0]
addr_select
dataIN_bytesel[2:0]
dataIN[63:0]
dataIN_BE[7:0]
dataIN_src_sel[1:0]
dataIN_cs
dataIN_byteID[1:0]
rcv0_fifo_ef
rcv0_fifo_prog_empty_flag
rcv1_fifo_ef
rcv1_fifo_prog_empty_flag
xmt0_fifo_ff
xmt0_fifo_prog_full_flag
xmt1_fifo_ff
xmt1_fifo_prog_full_flag
spci_done
cntl_data_in[63:0]
cntl_data_out[63:0]
cntl_wrt_nrd
cntl_addr[7:3]
cntl_be[7:0]
cntl_cs
data_out_byte_sel[2:0]
data_outCS
data_outDES[1:0]
data_outBE[7:0]
data_out[63:0]
interrupt_o
interrupt_i
user I/O (192)
gclk (4)
aclk (2)
user_clk
fpga_loc_sel[1:0]
fpga_bus_req[3:0]
Figure 10: PCI to Programmable Logic Interface Block Diagram
QL5064 QuickPCI Data Sheet Rev D
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