QL5064-33APB484I View Datasheet(PDF) - QuickLogic Corporation

Part Name

Description

MFG CO.

QL5064-33APB484I

66 MHz/64-bit PCI Master/Target with Embedded Programmable Logic and dual Port SRAM

QuickLogic Corporation 

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QL5064 QuickPCI Data Sheet

Table 1: PCI Back-End Interface Signals (Continued)

Symbol

I/O

Description

addr_select

O

DataIN Bus - (PCI - FPGA)

Selects which half of the 64-bit PCI address for a target transaction is

placed on the user_addr [32:0] bus.

0 - [35:3]

1 - 00000. [63:36]

data_IN [63:0]

I

Active High. A 64-bit bus connecting to the FIFO’s. Used by the FPGA to

obtain data being transferred from the PCI bus to the FPGA.

Active High. Data source select signals determines which FIFO is

connected to the data_in bus:

dataIN_src_sel[1:0]

dataIN_cs

O

00 Receive FIFO0

01 Receive FIFO1

10 Target Write post FIFO

11 Not defined (returns 0)

O

Active High. Chip select for read operations on the data_in bus. When

active, advances the pointer for the FIFO selected by dataIN_src_sel[1:0]

Active High. Indicates which byte lane is active for the current transfer

occurring on dataIN[63:0]

dataIN_BE[7:0]

dataIN_bytesel[2:0]

dataIN_BE[7]

dataIN[63:56]

dataIN_BE[6]

dataIN[55:48]

I

dataIN_BE[5]

dataIN[47:40]

dataIN_BE[4]

dataIN[39:32]

dataIN_BE[3]

dataIN[31:24]

dataIN_BE[2]

dataIN[23:16]

dataIN_BE[1]

dataIN[15:08]

dataIN_BE[0]

dataIN[07:00]

dataIN_BE[7:0] are shifted along with the data.

It is a number of bytes to barrel shift the 64-bit dataIN bus and the

dataIN_BE bus.

Active High. Tag bits for the DMA chain descriptor pointer. When active,

indicates that chain descriptor information is available at the output of

Receive FIFO0.

dataIN_byteID[1:0]

I

FIFO Status Signals

dataIN_byteID[1:0]

00 normal data

01 Descriptor dword 0 (PCI starting address)

10 Descriptor dword 1 (user defined)

11 Descriptor dword 2 (transfer count, et al.)

rcv0_fifo_ef

rcv0_fifo_prog_empty_flag

rcv1_fifo_ef

rcv1_fifo_prog_empty_flag

xmt0_fifo_ff

xmt0_fifo_prog_full_flag

I Active High. Receive FIFO0 is empty

I

Active High. Receive FIFO0 contains a number of entries less than or

equal to the threshold set in register 0x68, bits 37:32

I Active High. Receive FIFO1 is empty.

I

Active High. Receive FIFO 1 contains a number of entries less than or

equal to the threshold set in register 0x68, bits 45:40.

I Active High. Transmit FIFO0 is full.

I

Active High. Transmit FIFO0 contains a number of entries greater than or

equal to the threshold set in register 0x68, bits 53:48.

(Sheet 2 of 4)

QL5064 QuickPCI Data Sheet Rev D

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