QL5064-33APB484I View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
QL5064-33APB484I
QuickLogic Corporation
'QL5064-33APB484I' PDF : 37 Pages View PDF
QL5064 QuickPCI Data Sheet
19.0 Configuration Space
Defaults for most configuration space parameters can be programmed into the Via-Link antifuse based
configuration region in the device. Also, by fully supporting the extended configuration space region
beyond the 40(hex), the full enhanced feature set of the PCI bus is available to the user.
31
16 15
Device ID
R
AF
Status
M
AF
0
Vendor ID R
AF
Command
M
AF
BIST RW
Class Code
Header R
Type AF
M
AF
R
AF
Latency
RW
Timer
Revision ID R AF
Cashe Line
RW
Size
M
AF
M
AF
Base Address Registers
M
AF
M
AF
M
AF
Cardbus CIS Pointer
R
AF
Subsystem ID
R
AF
Subsystem Vendor ID
R
AF
Expansion ROM Base Address
M
AF
Reserved
R
AF
Cap. Ptr
R
AF
Max_Lat R AF
Reserved
R
AF
Min_Gnt R AF
Interrupt R
Pin
AF
Interrupt
RW
Line
FPGA Controlled
using
BARCS[7]
R
AF
Read only
antifuse program
M
AF
Read / Write masked by antifuses
RW Read / Write
00h
04h
08h
0Ch
10h
14h
18h
1Ch
20h
24h
28h
2Ch
30h
34h
38h
3Ch
40h
FF
Figure 11: Configuration Space Block Diagram
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