QL5064-33APB484I View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
QL5064-33APB484I
QuickLogic Corporation
'QL5064-33APB484I' PDF : 37 Pages View PDF
QL5064 QuickPCI Data Sheet
Table 1: PCI Back-End Interface Signals (Continued)
Symbol
I/O
Description
Interrupt Control
interrupt_i
O
interrupt_o
I
Master Arbitration Control
Active High and level sensitive. When active and not masked, asserts a
PCI interrupt.
Active High. Indicates an interrupt is pending for the FPGA to service.
fpga_loc_sel[1:0]
FPGA arbitration select. If the FPGA has control of the master-modeling
arbitration, these bits determine which DMA channel should initiate a DMA
transfer after the next arbitration cycle. Has relationship to pci_clk.
O
00 => Receive channel 1 has access to the bus
01 => Receive channel 0 has access to the bus
10 => Transmit channel 1 has access to the bus
11 => Transmit channel 0 has access to the bus
Active High. Master request status. Indicates that the respective master
has need to access the PCI bus. Has relationship to pci_clk.
fpga_bus_req[3:0]
I
fpga_bus_req[0] = receive channel 1
fpga_bus_req[1] = receive channel 0
fpga_bus_req[2] = transmit channel 1
fpga_bus_req[3] = transmit channel 0
(Sheet 4 of 4)
QL5064 QuickPCI Data Sheet Rev D
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