RC28F320J3F75 View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
RC28F320J3F75
Micron Technology
'RC28F320J3F75' PDF : 66 Pages View PDF
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
7.0
AC Characteristics
Timing symbols used in the timing diagrams within this document conform to the
following convention.
Figure 7: Timing Signal Naming Convention
t ELQV
Source Signal
Source State
Target State
Target Signal
Table 10: Timing Signal Name Decoder
Signal
Code
Address
A
Data - Read
Q
Data - Write
D
Chip Enable (CE)
E
Output Enable (OE#)
G
Write Enable (WE#)
W
Status (STS)
R
Reset (RP#)
P
Byte Enable (BYTE#)
F
Erase/Program/Block Lock
Enable (VPEN)
V
High
Low
High-Z
Low-Z
Valid
Invalid
State
Code
H
L
Z
X
V
I
Note:
Exceptions to this convention include tACC and tAPA. tACC is a generic timing symbol that
refers to the aggregate initial-access delay as determined by tAVQV, tELQV, and tGLQV
(whichever is satisfied last) of the flash device. tAPA is specified in the flash device’s
data sheet, and is the address-to-data delay for subsequent page-mode reads.
Jan 2011
208032-03
Datasheet
23
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