Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
7.1
Read Specifications
Table 11: Read Operations
Asynchronous Specifications VCC = 2.7 V–3.6 V (3) and VCCQ = 2.7 V–3.6 V(3)
#
Sym
Parameter
Density
Min
Max
Unit
Notes
R1
tAVAV
R2
tAVQV
R3
tELQV
R4
tGLQV
Read/Write Cycle Time
Address to Output Delay
CEX to Output Delay
OE# to Non-Array Output Delay
75
—
ns
—
75
ns
All
—
75
ns
—
25
ns
32 Mbit
—
150
R5
tPHQV
RP# High to Output Delay
64 Mbit
—
128 Mbit
—
180
ns
210
R6
tELQX
CEX to Output in Low Z
R7
tGLQX
OE# to Output in Low Z
R8
tEHQZ
CEX High to Output in High Z
R9
tGHQZ
OE# High to Output in High Z
R10 tOH
Output Hold from Address, CEX, or OE#
Change, Whichever Occurs First
R11 tELFL/tELFH CEX Low to BYTE# High or Low
All
R12 tFLQV/tFHQV BYTE# to Output Delay
R13
tFLQZ
BYTE# to Output in High Z
R14
tEHEL
CEx High to CEx Low
R15
tAPA
Page Address Access Time
R16
tGLQV
OE# to Array Output Delay
0
—
ns
0
—
ns
—
25
ns
—
15
ns
0
—
ns
—
10
ns
—
1
µs
—
1
µs
0
—
ns
—
25
ns
—
25
ns
1,2
1,2
1,2
1,2,4
1,2
1,2
1,2
1,2,5
1,2,5
1,2,5
1,2,5
1,2,5
1,2,5
1,2
1,2,5
1,2,5
5, 6
1,2,4
Notes:
1.
CEX low is defined as the
combination of pins CE0,
combination of pins CE0, CE1 and CE2 that enable the
CE1, and CE2 that disable the device (see Table 17,
device.
“Chip
ECEnXahbilgeh
is defined as the
Truth Table for
32-
, 64-, 128-Mb” on page 30).
2.
See AC Input/Output Reference Waveforms for the maximum allowable input slew rate.
3.
4.
TOSaeEe#blFemigafuyorrbee3d12e3-la,,y6“eAd4C-u,pI1tno2pt8uE-LtQM/VO-btuG”LtoQpVnuatpftRaeregtfeheer3ef0anl)lcinwegithWeodaugtevieomffpoCarEcmXt o(”sneoteEnLnQopVt.aeg1ean2d9TaanbdleFig1u7r,e“C1h4i,p“ETrnaanbslieenTrtuth
Equivalent Testing Load Circuit” on page 29 for testing characteristics.
5.
Sampled, not 100% tested.
6.
For devices configured to standard word/byte read mode, R15 (tAPA) will equal R2 (tAVQV).
Datasheet
24
Jan 2011
208032-03