RC28F320J3F75 View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
RC28F320J3F75
Micron Technology
'RC28F320J3F75' PDF : 66 Pages View PDF
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
8.0
Bus Interface
This section provides an overview of Bus operations. The on-chip Write State Machine
(WSM) manages all erase and program algorithms. The system CPU provides control of
all in-system read, write, and erase operations through the system bus. All bus cycles
to or from the flash memory conform to standard microprocessor bus cycles. Table 16
summarizes the necessary states of each control signal for different modes of
operations.
Table 16: Bus Operations
Mode
RP#
CEx(1) OE#(2) WE#(2)
VPEN
DQ15:0(3)
STS
(Default
Mode)
Notes
Async., Status, Query and
Identifier Reads
Output Disable
Standby
Reset/Power-down
Command Writes
Array Writes
VIH
Enabled
VIL
VIH
Enabled
VIH
VIH
Disabled
X
VIL
X
X
VIH
Enabled
VIH
VIH
Enabled
VIH
VIH
X
DOUT
VIH
X
High Z
X
X
High Z
X
X
High Z
VIL
X
DIN
VIL
VPENH
X
High Z
4,6
High Z
—
High Z
—
High Z
—
High Z
6,7
VIL
5,8
Notes:
1.
See Table 17 for valid CEx configurations.
2.
OE# and WE# should never be asserted simultaneously. If done so, OE# overrides WE#.
3.
DQ refers to DQ[7:0] when BYTE# is low and DQ[15:0] if BYTE# is high.
4.
Refer to DC characteristics. When VPEN ≤ VPENLK, memory contents can be read but not altered.
5.
X should be VIL or VIH for the control pins and VPENLK or VPENH for VPEN. For outputs, X should be VOL or VOH.
6.
In default mode, STS is VOL when the WSM is executing internal block erase, program, or a lock-bit configuration
algorithm. It is VOH (pulled up by an external pull up resistance ≈ 10k) when the WSM is not busy, in block erase suspend
mode (with programming inactive), program suspend mode, or reset power-down mode.
7.
See Section 11.0, “Device Command Codes†on page 47 for valid DIN (user commands) during a Write
operation.
8.
Array writes are either program or erase operations.
Table 17: Chip Enable Truth Table for 32-, 64-, 128-Mb
CE2
CE1
CE0
VIL
VIL
VIL
VIL
VIL
VIH
VIL
VIH
VIL
VIL
VIH
VIH
VIH
VIL
VIL
VIH
VIL
VIH
VIH
VIH
VIL
VIH
VIH
VIH
Note: For single-chip applications, CE2 and CE1 can be connected to VSS.
DEVICE
Enabled
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Disabled
Datasheet
30
Jan 2011
208032-03
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