RC28F320J3F75 View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
RC28F320J3F75
Micron Technology
'RC28F320J3F75' PDF : 66 Pages View PDF
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
Table 14: Reset Specifications
#
Symbol
Parameter
Min
Max
Unit
Notes
RP# Pulse Low Time
RP# is asserted during block erase,
P1
tPLPH
(If RP# is tied to VCC, this
specification is not
program or lock-bit configuration
operation
25
—
µs
1
applicable)
RP# is asserted during read
100
—
ns
1
P2
tPHRH
RP# High to Reset during Block Erase, Program, or Lock-Bit
Configuration
—
100
ns
1,2
P3
tVCCPH Vcc Power Valid to RP# de-assertion (high)
60
—
µs
—
Notes:
1.
These specifications are valid for all product versions (packages and speeds).
2.
A reset time, tPHQV, is required from the latter of STS (in RY/BY# mode) or RP# going high until outputs are valid.
7.4
AC Test Conditions
Figure 13: AC Input/Output Reference Waveform
VCCQ
Input
0.0
VCCQ/2
Test Points
VCCQ/2 Output
Note: AC test inputs are driven at VCCQ for a Logic "1" and 0.0 V for a Logic "0." Input timing begins, and output timing ends, at
VCCQ/2 V (50% of VCCQ). Input rise and fall times (10% to 90%) < 5 ns.
Figure 14: Transient Equivalent Testing Load Circuit
Device
Under Test
Out
CL
Note: CL Includes Jig Capacitance
Table 15: Test Configuration
Test Configuration
VCCQ = VCCQMIN
CL (pF)
30
Jan 2011
208032-03
Datasheet
29
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