RC28F320J3F75 View Datasheet(PDF) - Micron Technology
Part Name
Description
MFG CO.
RC28F320J3F75
Micron Technology
'RC28F320J3F75' PDF : 66 Pages View PDF
Numonyx® Embedded Flash Memory (J3 65 nm) Single Bit per Cell (SBC)
Table 12: Write Operations
#
Symbol
Parameter
Density
Valid for All
Speeds
Min
Max
Unit
Notes
32 Mbit
150
—
W1
tPHWL (tPHEL) RP# High Recovery to WE# (CEX) Going Low 64 Mbit
180
—
128 Mbit
210
—
1,2,3,4
W2
tELWL (tWLEL) CEX (WE#) Low to WE# (CEX) Going Low
0
—
1,2,3,5
W3
tWP
Write Pulse Width
60
—
1,2,3,5
W4 tDVWH (tDVEH) Data Setup to WE# (CEX) Going High
50
—
1,2,3,6
W5 tAVWH (tAVEH) Address Setup to WE# (CEX) Going High
55
—
1,2,3,6
W6 tWHEH (tEHWH) CEX (WE#) Hold from WE# (CEX) High
W7 tWHDX (tEHDX) Data Hold from WE# (CEX) High
W8
tWHAX (tEHAX) Address Hold from WE# (CEX) High
0
—
ns
1,2,3
0
—
1,2,3
All
0
—
1,2,3
W9
tWPH
Write Pulse Width High
30
—
1,2,3,7
W11 tVPWH (tVPEH) VPEN Setup to WE# (CEX) Going High
0
—
1,2,3,4
W12 tWHGL (tEHGL) Write Recovery before Read
35
—
1,2,3,8
W13 tWHRL (tEHRL) WE# (CEX) High to STS Going Low
—
500
1,2,3,9
W15
tQVVL
VPEN Hold from Valid SRD, STS Going High
0
—
1,2,3,4,
9,10
Notes:
1.
CEX low is defined as the
combination of pins CE0,
combination of pins CE0, CE1,
CE1, and CE2 that disable the
daenvdicCeE(2setehaTtaebnlaebl1e 7th,e“dCehviicpe.ECnEaXbhlieghTirsudtehfinTeadbalsethfoer
32-, 64-, 128-Mb” on page 30).
2.
Read timing characteristics during block erase, program, and lock-bit configuration operations are the same as during
read-only operations. Refer to AC Characteristics–Read-Only Operations.
3.
A write operation can be initiated and terminated with either CEX or WE#.
4.
Sampled, not 100% tested.
5.
Write pulse width (tWP) is defined from CEX or WE# going low (whichever goes low last) to CEX or WE# going high
6.
(whichever goes high first). Hence,
Refer to Table 18, “Enhanced
CtWoPn=fitgWuLWraHt=iotnELERHe=gitsWtLeEHr”=otnELWpHa.ge
32
for
valid
AIN
and
DIN
for
block
erase,
program, or lock-bit configuration.
7.
Write pulse width high (tWPH) is defined from CEX or WE# going high (whichever goes high first) to CEX or WE# going
low (whichever goes low first). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL.
8.
For array access, tAVQV is required in addition to tWHGL for any accesses after a write.
9.
STS timings are based on STS configured in its RY/BY# default mode.
10.
VPEN should be held at VPENH until determination of block erase, program, or lock-bit configuration success (SR[5:3,1]
= 0).
Datasheet
26
Jan 2011
208032-03
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