SAA7392HLM2B View Datasheet(PDF) - Philips Electronics
Part Name
Description
MFG CO.
'SAA7392HLM2B' PDF : 76 Pages View PDF
Philips Semiconductors
Channel encoder/decoder CDR60
Preliminary specification
SAA7392
7.17.6 WOBBLE CONFIGURATION REGISTER 2 (WOBBLECONFIG2)
Table 140 Wobble Configuration Register 2 (address 28H) - WRITE
7
6
5
4
3
−
−
PLLLBW.2 PLLLBW.1 PLLLBW.0
2
PLLHBW.2
1
PLLHBW.1
0
PLLHBW.0
Table 141 Description of WobbleConfig2 bits
BIT
SYMBOL
DESCRIPTION
7
−
These 2 bits are reserved.
6
−
5
PLLLBW.2 These 3 bits select the PLL low-pass bandwidth; see Table 142.
4
PLLLBW.1
3
PLLLBW.0
2
PLLHBW.2 These 3 bits select the PLL high-pass bandwidth; see Table 142.
1
PLLHBW.1
0
PLLHBW.0
Table 142 Selection of the PLL high/low-pass bandwidth
PLLLBW.2
PLLHBW.2
0
0
0
0
1
1
1
1
PLLLBW.1
PLLHBW.1
0
0
1
1
0
0
1
1
PLLLBW.0
PLLHBW.0
HIGH/LOW-PASS BANDWIDTH
0
43 kHz for 4.26 MHz system clock
1
21.5 kHz for 4.26 MHz system clock
0
10.7 kHz for 4.26 MHz system clock
1
5.4 kHz for 4.26 MHz system clock
0
2.7 kHz for 4.26 MHz system clock
1
1.35 kHz for 4.26 MHz system clock
0
670 Hz for 4.26 MHz system clock
1
350 Hz for 4.26 MHz system clock
2000 Mar 21
61
Share Link: 
