Philips Semiconductors
Channel encoder/decoder CDR60
Preliminary specification
SAA7392
7.17.10 ATIP DATA REGISTER (ATIPDATA)
The upper 16 bits of the ATIP data can be obtained from this register by carrying out consecutive read operations.
Table 149 ATIP Data Register (address 2CH) - READ
7
6
5
4
3
2
1
0
ATIPData.23 ATIPData.22 ATIPData.21 ATIPData.20 ATIPData.19 ATIPData.18 ATIPData.17 ATIPData.16
ATIPData.15 ATIPData.14 ATIPData.13 ATIPData.12 ATIPData.11 ATIPData.10 ATIPData.9 ATIPData.8
Table 150 Description of ATIPData bits
BIT
7 to 0
7 to 0
SYMBOL
ATIPData<23:16>
ATIPData<15:8>
DESCRIPTION
most significant byte of ATIP data
penultimate byte of ATIP data
7.17.11 ATIP DATA END REGISTER (ATIPDATAEND)
Table 151 ATIP Data End Register (address 2DH) - READ
7
6
5
4
3
ATIPData.7 ATIPData.6 ATIPData.5 ATIPData.4 ATIPData.3
2
ATIPData.2
1
ATIPData.1
0
ATIPData.0
Table 152 Description of ATIPDataEnd bits
BIT
7 to 0
SYMBOL
ATIPData<7:0>
DESCRIPTION
least significant byte of ATIP data
7.17.12 WOBBLE PEAK STATUS REGISTER (WOBBLESTATUS)
Table 153 Wobble Peak Status Register (address 2EH) - READ
7
WPPV.7
6
WPPV.6
5
WPPV.5
4
WPPV.4
3
WPPV.3
2
WPPV.2
1
WPPV.1
0
WPPV.0
Table 154 Description of WobbleStatus bits
BIT
7 to 0
SYMBOL
DESCRIPTION
WPPV<7:0> Peak value of the bit signal recovered by the Wobble processor.
7.17.13 ATIP ERROR REGISTER (ATER)
This register is an unbuffered counter and is incremented on every ATIP code CRC error. When the register reaches 255
it will hold and is reset by being read.
Table 155 ATIP Error Register (address 38H) - READ
7
ATER.7
6
ATER.6
5
ATER.5
4
ATER.4
3
ATER.3
2
ATER.2
1
ATER.1
0
ATER.0
2000 Mar 21
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