Philips Semiconductors
Channel encoder/decoder CDR60
Preliminary specification
SAA7392
9 OPERATING CHARACTERISTICS
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supply
VDDD
VDDA
VDDE
IDD
supply voltage (core/pad ring)
supply voltage (analog)
supply voltage (pad output drivers)
supply current
Digital inputs
3.0
3.3
3.6
V
3.0
3.3
3.6
V
3.0
3.3
3.6
V
−
200
−
mA
SCL (CMOS)
VIL
LOW-level input voltage
VIH
HIGH-level input voltage
ILI
input leakage current
Ci
input capacitance
Vi = 0 to VDD
−
−
0.7VDD −
−10
−
−
−
0.3VDD V
5.0
V
+10
µA
10
pF
TEST1, TEST2, OTD, MUXSWI, PANIC, PORE, WRI, RDI, ALE, CSI, PCAIN, DATAI, SUB, SFSY, T2 AND T1
VIL
LOW-level input voltage
VIH
HIGH-level input voltage
ILI
input leakage current
Ci
input capacitance
Vi = 0 to VDD
−
−
2.0
−
−10
−
−
−
0.8
V
5.0
V
+10
µA
10
pF
Digital outputs
W441, ATPSYC, CL1, INT, STOPCK, V4, EBUOUT, SYNC, FLAG, DATAO, RCK, LASERON, XEFM, EFMDATA,
CFLG AND MEAS1
VOL
LOW-level output voltage
VOH
HIGH-level output voltage
CL
load capacitance
tr
output rise time
tf
output fall time
IOL = 4 mA
IOH = −4 mA
0.4 to (VDD − 0.4);
CL = 20 pF
(VDD − 0.4) to 0.4;
CL = 20 pF
−
−
0.85VDD −
−
−
−
−
−
−
0.4
V
−
V
20
pF
20
ns
20
ns
MOTO1 (3-STATE)
VOL
LOW-level output voltage
VOH
HIGH-level output voltage
CL
load capacitance
tr
output rise time
tf
output fall time
ILI
3-state leakage current
IOL = 4 mA
IOH = −4 mA
0.4 to (VDD − 0.4);
CL = 20 pF
(VDD − 0.4) to 0.4;
CL = 20 pF
Vi = 0 to VDD
−
−
0.85VDD −
−
−
−
−
−
−
−10
−
0.4
V
−
V
20
pF
20
ns
20
ns
+10
µA
Digital I/O
DA7 TO DA0, WCLK, BCLK AND MOTO2/T3
VIL
LOW-level input voltage
VIH
HIGH-level input voltage
−
−
0.7VDD −
0.3VDD V
5.0
V
2000 Mar 21
65