SAA7392HLM2B View Datasheet(PDF) - Philips Electronics
Part Name
Description
MFG CO.
'SAA7392HLM2B' PDF : 76 Pages View PDF
Philips Semiconductors
Channel encoder/decoder CDR60
Preliminary specification
SAA7392
7.17.7 ATIP STATUS REGISTER (ATIPSTATUS)
Table 143 ATIP Status Register (address 29H) - READ
7
6
5
4
3
ATIPReady
Busy
CRCOK
−
−
2
1
0
−
SyncErr
OIS
Table 144 Description of ATIPStatus bits
BIT
SYMBOL
DESCRIPTION
7
ATIPReady If ATIPReady = 0, then ATIP data is not ready. If ATIPReady = 1, then ATIP data is ready
for read. Can also be an interrupt source.
6
Busy If Busy = 0, then ATIP data is not being read. If Busy = 1, then sub-CPU is busy reading
ATIP data.
5
CRCOK If CRCOK = 0, then CRC check is not OK. If CRCOK = 1, then CRC check is OK.
4
−
These 3 bits are reserved.
3
−
2
−
1
SyncErr If SyncErr = 1, then detected sync is not in-phase with the interpolated sync. Resync will
be done on next detected sync.
0
OIS
If OIS = 1, then sync has been interpolated, no detected sync.
7.17.8 WOBBLE FREQUENCY REGISTER 1 (WOBBLEFREQ1)
Table 145 Wobble Frequency Register 1 (address 2AH) - WRITE/READ
7
6
5
4
3
2
PLLFreq.15 PLLFreq.14 PLLFreq.13 PLLFreq.12 PLLFreq.11 PLLFreq.10
1
PLLFreq.9
0
PLLFreq.8
Table 146 Description of WobbleFreq1 bits
BIT
7 to 0
SYMBOL
PLLFreq<15:8>
DESCRIPTION
These 8 bits form the most significant byte of the PLL frequency.
7.17.9 WOBBLE FREQUENCY REGISTER 2 (WOBBLEFREQ2)
Table 147 Wobble Frequency Register 2 (address 2BH) - READ/WRITE
7
PLLFreq.7
6
PLLFreq.6
5
PLLFreq.5
4
PLLFreq.4
3
PLLFreq.3
2
PLLFreq.2
1
PLLFreq.1
0
PLLFreq.0
Table 148 Description of WobbleFreq2 bits
BIT
7 to 0
SYMBOL
PLLFreq<7:0>
DESCRIPTION
These 8 bits form the least significant byte of the PLL frequency.
2000 Mar 21
62
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