ST7FLITE02Y1B6 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST7FLITE02Y1B6
STMicroelectronics
'ST7FLITE02Y1B6' PDF : 124 Pages View PDF
ST7LITE0xY0, ST7LITESxY0
13.7 EMC (ELECTROMAGNETIC COMPATIBILITY) CHARACTERISTICS
Susceptibility tests are performed on a sample ba-
sis during product characterization.
13.7.1 Functional EMS (Electro Magnetic
Susceptibility)
Based on a simple running application on the
product (toggling two -+LEDs through I/O ports),
the product is stressed by two electro magnetic
events until a failure occurs (indicated by the
LEDs).
■ ESD: Electro-Static Discharge (positive and
negative) is applied on all pins of the device until
a functional disturbance occurs. This test
conforms with the IEC 1000-4-2 standard.
■ FTB: A Burst of Fast Transient voltage (positive
and negative) is applied to VDD and VSS through
a 100pF capacitor, until a functional disturbance
occurs. This test conforms with the IEC 1000-4-
4 standard.
A device reset allows normal operations to be re-
sumed. The test results are given in the table be-
low based on the EMS levels and classes defined
in application note AN1709.
13.7.1.1 Designing hardened software to avoid
noise problems
EMC characterization and optimization are per-
formed at component level with a typical applica-
tion environment and simplified MCU software. It
should be noted that good EMC performance is
highly dependent on the user application and the
software in particular.
Therefore it is recommended that the user applies
EMC software optimization and prequalification
tests in relation with the EMC level requested for
his application.
Software recommendations:
The software flowchart must include the manage-
ment of runaway conditions such as:
– Corrupted program counter
– Unexpected reset
– Critical Data corruption (control registers...)
Prequalification trials:
Most of the common failures (unexpected reset
and program counter corruption) can be repro-
duced by manually forcing a low state on the RE-
SET pin or the Oscillator pins for 1 second.
To complete these trials, ESD stress can be ap-
plied directly on the device, over the range of
specification values. When unexpected behaviour
is detected, the software can be hardened to pre-
vent unrecoverable errors occurring (see applica-
tion note AN1015).
Symbol
Parameter
Conditions
VFESD
VFFTB
Voltage limits to be applied on any I/O pin to induce a VDD=5V, TA=+25°C, fOSC=8MHz
functional disturbance
conforms to IEC 1000-4-2
Fast transient voltage burst limits to be applied
through 100pF on VDD and VDD pins to induce a func-
tional disturbance
VDD=5V, TA=+25°C, fOSC=8MHz
conforms to IEC 1000-4-4
Level/
Class
2B
3B
13.7.2 EMI (Electromagnetic interference)
Based on a simple application running on the
product (toggling two LEDs through the I/O ports),
the product is monitored in terms of emission. This
Table 20: EMI emissions
emission test is in line with the norm
SAE J 1752/3 which specifies the board and the
loading of each pin.
Symbol
Parameter
Conditions
Monitored
Frequency Band
SEMI Peak level
VDD=5V, TA=+25°C,
SO16 package,
0.1MHz to 30MHz
30MHz to 130MHz
conforming to SAE J 1752/3 130MHz to 1GHz
SAE EMI Level
Note:
1. Data based on characterization results, not tested in production.
Max vs. [fOSC/fCPU]
1/4MHz 1/8MHz
8
14
27
32
26
28
3.5
4
Unit
dBµV
-
93/124
1
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