ST7FLU05MCE View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
ST7FLU05MCE
STMicroelectronics
'ST7FLU05MCE' PDF : 124 Pages View PDF
I/O ports
ST7LUS5, ST7LU05, ST7LU09
9.6
I/O port implementation
The hardware implementation on each I/O port depends on the settings in the DDR and OR
registers and specific feature of the I/O port such as ADC Input or true open drain.
Switching these I/O ports from one state to another should be done in a sequence that
prevents unwanted side effects. Recommended safe transitions are illustrated in Figure 36.
Other transitions are potentially risky and should be avoided, since they are likely to present
unwanted side-effects such as spurious interrupt generation.
Figure 28. Interrupt I/O port state transitions
01
00
10
11
Input
Input
Output
) floating/pull-up floating open-drain
t(s interrupt (reset state)
Output
push-pull
c XX = DDR, OR
rodu ) The I/O port register configurations are summarized in the following table:
P t(s Table 31.
solete roduc Port
Port configuration
Pin name
Input (DDR=0)
OR = 0
OR = 1
Output (DDR=1)
OR = 0
OR = 1
) - Ob lete P Port A
PA0:2,
PA4:5
PA3
Floating
-
Pull-up interrupt Open drain
-
Open drain
Push-pull
Push-pull
t(s so Note: After reset, to configure PA3 as a general purpose output, the application has to
c b program the MUXCR0 and MUXCR1 registers. See Section 6.4 on page 42.
rodu - O Table 32. I/O port register map and reset values
P t(s) Address (Hex.) Register label 7
6
5
4
3
2
1
0
lete uc 0000h
PADR
Reset value
MSB
0
0
0
0
0
0
LSB
0
0
so rod 0001h
PADDR
Reset value
MSB
0
0
0
0
1
0
LSB
0
0
OObbsolete P0002h
PAOR
Reset value
MSB
0
0
0
0
0
0
LSB
1
0
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